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Nathan W. Ha

Examiner (ID: 14314)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
2125
Issued Applications
1816
Pending Applications
114
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16262474 [patent_doc_number] => 10753902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Chipless and wireless sensor circuit and sensor tag [patent_app_type] => utility [patent_app_number] => 16/148590 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6706 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148590
Chipless and wireless sensor circuit and sensor tag Sep 30, 2018 Issued
Array ( [id] => 15581023 [patent_doc_number] => 10580906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Semiconductor device comprising a PN junction diode [patent_app_type] => utility [patent_app_number] => 16/148285 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3500 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148285
Semiconductor device comprising a PN junction diode Sep 30, 2018 Issued
Array ( [id] => 15375953 [patent_doc_number] => 10529704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Auxiliary gate antenna diodes [patent_app_type] => utility [patent_app_number] => 16/148323 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148323
Auxiliary gate antenna diodes Sep 30, 2018 Issued
Array ( [id] => 14938435 [patent_doc_number] => 20190304856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => TEST ELEMENT GROUP AND SEMICONDUCTOR WAFER INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/148424 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148424
Test element group and semiconductor wafer including the same Sep 30, 2018 Issued
Array ( [id] => 13849227 [patent_doc_number] => 20190028098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SEMICONDUCTOR DEVICE FOR DISPLAY DRIVER IC STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/140894 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140894 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140894
Semiconductor device for display driver IC structure Sep 24, 2018 Issued
Array ( [id] => 15889625 [patent_doc_number] => 10651168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => RF amplifier package with biasing strip [patent_app_type] => utility [patent_app_number] => 16/135163 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135163 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135163
RF amplifier package with biasing strip Sep 18, 2018 Issued
Array ( [id] => 16172907 [patent_doc_number] => 10714485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Semiconductor device which includes Fins [patent_app_type] => utility [patent_app_number] => 16/126875 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 44 [patent_no_of_words] => 12423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126875
Semiconductor device which includes Fins Sep 9, 2018 Issued
Array ( [id] => 13785461 [patent_doc_number] => 20190006269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => Enhanced Thermal Transfer in a Semiconductor Structure [patent_app_type] => utility [patent_app_number] => 16/121721 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121721
Enhanced thermal transfer in a semiconductor structure Sep 4, 2018 Issued
Array ( [id] => 16692146 [patent_doc_number] => 20210074625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => GRAPHITE-LAMINATED CHIP-ON-FILM-TYPE SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT DISSIPATION AND ELECTROMAGNETIC WAVE SHIELDING FUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/640643 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16640643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/640643
Graphite-laminated chip-on-film-type semiconductor package having improved heat dissipation and electromagnetic wave shielding functions Aug 20, 2018 Issued
Array ( [id] => 13629855 [patent_doc_number] => 20180366480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => EEPROM DEVICE [patent_app_type] => utility [patent_app_number] => 16/103725 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103725 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103725
EEPROM device Aug 13, 2018 Issued
Array ( [id] => 13613819 [patent_doc_number] => 20180358459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => SELF-ALIGNED SHALLOW TRENCH ISOLATION AND DOPING FOR VERTICAL FIN TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/053123 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/053123
Self-aligned shallow trench isolation and doping for vertical fin transistors Aug 1, 2018 Issued
Array ( [id] => 15315471 [patent_doc_number] => 10522451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Fan-out semiconductor package [patent_app_type] => utility [patent_app_number] => 16/035192 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 11697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035192
Fan-out semiconductor package Jul 12, 2018 Issued
Array ( [id] => 18349349 [patent_doc_number] => 20230137460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => METHOD FOR PRODUCING A VIA IN A CARRIER LAYER PRODUCED FROM A CERAMIC AND CARRIER LAYER HAVING A VIA [patent_app_type] => utility [patent_app_number] => 16/628579 [patent_app_country] => US [patent_app_date] => 2018-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16628579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/628579
METHOD FOR PRODUCING A VIA IN A CARRIER LAYER PRODUCED FROM A CERAMIC AND CARRIER LAYER HAVING A VIA Jul 3, 2018 Abandoned
16/020345 METHOD FOR PROCESSING A SEMICONDUCTOR WAFER USING NON-CONTACT ELECTRICAL MEASUREMENTS INDICATIVE OF AT LEAST ONE TIP-TO-SIDE SHORT OR LEAKAGE, AT LEAST ONE SIDE-TO-SIDE SHORT OR LEAKAGE, AND AT LEAST ONE VIA-CHAMFER SHORT OR LEAKAGE, WHERE SUCH MEASUREMENTS ARE OBT Jun 26, 2018 Abandoned
Array ( [id] => 13893475 [patent_doc_number] => 10199290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-05 [patent_title] => Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage [patent_app_type] => utility [patent_app_number] => 16/019942 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 209 [patent_figures_cnt] => 314 [patent_no_of_words] => 45773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019942 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019942
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage Jun 26, 2018 Issued
Array ( [id] => 13730789 [patent_doc_number] => 20180369862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => MICROFABRICATED ULTRASONIC TRANSDUCER HAVING INDIVIDUAL CELLS WITH ELECTRICALLY ISOLATED ELECTRODE SECTIONS [patent_app_type] => utility [patent_app_number] => 16/012999 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/012999
Microfabricated ultrasonic transducer having individual cells with electrically isolated electrode sections Jun 19, 2018 Issued
Array ( [id] => 13420271 [patent_doc_number] => 20180261678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => ATOMIC LAYER DEPOSITION METHODS AND STRUCTURES THEREOF [patent_app_type] => utility [patent_app_number] => 15/978546 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978546
Atomic layer deposition methods and structures thereof May 13, 2018 Issued
Array ( [id] => 13419933 [patent_doc_number] => 20180261509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => METHODS FOR FORMING THE ISOLATION STRUCTURE OF THE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/975168 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975168
Methods for forming the isolation structure of the semiconductor device and semiconductor devices May 8, 2018 Issued
Array ( [id] => 15857445 [patent_doc_number] => 10644021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Dense arrays and charge storage devices [patent_app_type] => utility [patent_app_number] => 15/971293 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 169 [patent_no_of_words] => 43089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971293
Dense arrays and charge storage devices May 3, 2018 Issued
Array ( [id] => 16479568 [patent_doc_number] => 10854522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas [patent_app_type] => utility [patent_app_number] => 15/942475 [patent_app_country] => US [patent_app_date] => 2018-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 209 [patent_figures_cnt] => 314 [patent_no_of_words] => 45493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942475 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942475
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas Mar 30, 2018 Issued
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