Search

Nathan W. Ha

Examiner (ID: 14314)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
2125
Issued Applications
1816
Pending Applications
114
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12631254 [patent_doc_number] => 20180102248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => MATERIAL DEPOSITION FOR HIGH ASPECT RATIO STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/831342 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831342
Material deposition for high aspect ratio structures Dec 3, 2017 Issued
Array ( [id] => 14738441 [patent_doc_number] => 10388630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture [patent_app_type] => utility [patent_app_number] => 15/829428 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829428
Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture Nov 30, 2017 Issued
Array ( [id] => 14738377 [patent_doc_number] => 10388598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Interposer, semiconductor package structure, and semiconductor process [patent_app_type] => utility [patent_app_number] => 15/818337 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 9052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818337
Interposer, semiconductor package structure, and semiconductor process Nov 19, 2017 Issued
Array ( [id] => 12243355 [patent_doc_number] => 20180076218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/813985 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9800 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813985
Semiconductor device and method of manufacturing the same Nov 14, 2017 Issued
Array ( [id] => 12236151 [patent_doc_number] => 20180069014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/811432 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12051 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811432
SEMICONDUCTOR DEVICE Nov 12, 2017 Abandoned
Array ( [id] => 14641007 [patent_doc_number] => 10365240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Flexible and stretchable sensors formed by patterned spalling [patent_app_type] => utility [patent_app_number] => 15/811265 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5463 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811265
Flexible and stretchable sensors formed by patterned spalling Nov 12, 2017 Issued
Array ( [id] => 14753075 [patent_doc_number] => 20190259711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME AND WIRELESS COMMUNICATION APPARATUS [patent_app_type] => utility [patent_app_number] => 16/345429 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16345429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/345429
Semiconductor device and method for manufacturing the same and wireless communication apparatus Nov 1, 2017 Issued
Array ( [id] => 20276559 [patent_doc_number] => 12446348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Solid-state imaging element, manufacturing method, and electronic device [patent_app_type] => utility [patent_app_number] => 16/347432 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347432
Solid-state imaging element, manufacturing method, and electronic device Oct 31, 2017 Issued
Array ( [id] => 12181791 [patent_doc_number] => 20180040727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SELF-ALIGNED SHALLOW TRENCH ISOLATION AND DOPING FOR VERTICAL FIN TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/789620 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789620
Self-aligned shallow trench isolation and doping for vertical fin transistors Oct 19, 2017 Issued
Array ( [id] => 12188841 [patent_doc_number] => 20180047776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/725957 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 18011 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725957
Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus Oct 4, 2017 Issued
Array ( [id] => 12189371 [patent_doc_number] => 20180048306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'POWER CIRCUIT AND POWER MODULE USING MISFET HAVING CONTROL CIRCUIT DISPOSED BETWEEN GATE AND SOURCE' [patent_app_type] => utility [patent_app_number] => 15/724491 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 19962 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724491
Power circuit and power module using MISFET having control circuit disposed between gate and source Oct 3, 2017 Issued
Array ( [id] => 13769727 [patent_doc_number] => 10177213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Magnetic inductor stacks with multilayer isolation layers [patent_app_type] => utility [patent_app_number] => 15/724421 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724421
Magnetic inductor stacks with multilayer isolation layers Oct 3, 2017 Issued
Array ( [id] => 12154674 [patent_doc_number] => 20180025938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'Method of Forming Trenches with Different Depths' [patent_app_type] => utility [patent_app_number] => 15/722133 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722133
Method of forming trenches with different depths Oct 1, 2017 Issued
Array ( [id] => 12114969 [patent_doc_number] => 09870962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates' [patent_app_type] => utility [patent_app_number] => 15/719615 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 195 [patent_figures_cnt] => 300 [patent_no_of_words] => 53922 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719615 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719615
Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates Sep 28, 2017 Issued
Array ( [id] => 14125411 [patent_doc_number] => 10249569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor device having structure for improving voltage drop and device including the same [patent_app_type] => utility [patent_app_number] => 15/721020 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721020 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721020
Semiconductor device having structure for improving voltage drop and device including the same Sep 28, 2017 Issued
Array ( [id] => 14253417 [patent_doc_number] => 10276920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Package structure, electronic device and method of fabricating package structure [patent_app_type] => utility [patent_app_number] => 15/717976 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 6774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717976 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717976
Package structure, electronic device and method of fabricating package structure Sep 27, 2017 Issued
Array ( [id] => 13808361 [patent_doc_number] => 10181449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-15 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 15/717971 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717971
Semiconductor structure Sep 27, 2017 Issued
Array ( [id] => 13283373 [patent_doc_number] => 10153278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Fin-type field effect transistor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/717972 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717972
Fin-type field effect transistor structure and manufacturing method thereof Sep 27, 2017 Issued
Array ( [id] => 14110331 [patent_doc_number] => 20190096841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/717974 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717974
Package structure and method of manufacturing the same Sep 27, 2017 Issued
Array ( [id] => 13996607 [patent_doc_number] => 20190067461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/717975 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717975
Bipolar junction transistor and method for fabricating the same Sep 27, 2017 Issued
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