
Nathan W. Ha
Examiner (ID: 14314)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 2125 |
| Issued Applications | 1816 |
| Pending Applications | 114 |
| Abandoned Applications | 221 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12129835
[patent_doc_number] => 20180013421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'SEMICONDUCTOR DEVICE FOR DISPLAY DRIVER IC STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 15/392637
[patent_app_country] => US
[patent_app_date] => 2016-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10200
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392637
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/392637 | Semiconductor device for display driver IC structure | Dec 27, 2016 | Issued |
Array
(
[id] => 11532781
[patent_doc_number] => 20170092760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'Semiconductor Device with Non-Isolated Power Transistor with Integrated Diode Protection'
[patent_app_type] => utility
[patent_app_number] => 15/378458
[patent_app_country] => US
[patent_app_date] => 2016-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12850
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378458
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/378458 | Semiconductor device with non-isolated power transistor with integrated diode protection | Dec 13, 2016 | Issued |
Array
(
[id] => 12375924
[patent_doc_number] => 09960202
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-01
[patent_title] => Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus
[patent_app_type] => utility
[patent_app_number] => 15/370778
[patent_app_country] => US
[patent_app_date] => 2016-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 86
[patent_no_of_words] => 17181
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370778
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/370778 | Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus | Dec 5, 2016 | Issued |
Array
(
[id] => 11517555
[patent_doc_number] => 20170084627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'DENSE ARRAYS AND CHARGE STORAGE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/368396
[patent_app_country] => US
[patent_app_date] => 2016-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 86
[patent_figures_cnt] => 86
[patent_no_of_words] => 44400
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368396
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/368396 | Dense arrays and charge storage devices | Dec 1, 2016 | Issued |
Array
(
[id] => 12778825
[patent_doc_number] => 20180151443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => METHODS FOR FORMING THE ISOLATION STRUCTURE OF THE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/363112
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4937
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363112
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363112 | Methods for forming the isolation structure of the semiconductor device and semiconductor devices | Nov 28, 2016 | Issued |
Array
(
[id] => 12061875
[patent_doc_number] => 20170338219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/363221
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4268
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363221
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363221 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT | Nov 28, 2016 | Abandoned |
Array
(
[id] => 12779047
[patent_doc_number] => 20180151517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => SEMICONDUCTOR ELEMENT MOUNTING BOARD
[patent_app_type] => utility
[patent_app_number] => 15/362933
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362933
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362933 | Semiconductor element mounting board | Nov 28, 2016 | Issued |
Array
(
[id] => 11710813
[patent_doc_number] => 20170179311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION ELEMENT, AND PHOTOELECTRIC CONVERSION DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/363199
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7142
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363199
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363199 | Method of manufacturing photoelectric conversion element, photoelectric conversion element, and photoelectric conversion device | Nov 28, 2016 | Issued |
Array
(
[id] => 12778879
[patent_doc_number] => 20180151461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING
[patent_app_type] => utility
[patent_app_number] => 15/363267
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363267
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363267 | STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING | Nov 28, 2016 | Abandoned |
Array
(
[id] => 13214661
[patent_doc_number] => 10121706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-06
[patent_title] => Semiconductor structure including two-dimensional and three-dimensional bonding materials
[patent_app_type] => utility
[patent_app_number] => 15/361809
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4006
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361809
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/361809 | Semiconductor structure including two-dimensional and three-dimensional bonding materials | Nov 27, 2016 | Issued |
Array
(
[id] => 12102210
[patent_doc_number] => 09859311
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-02
[patent_title] => 'Storage gate protection'
[patent_app_type] => utility
[patent_app_number] => 15/362391
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3527
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362391
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362391 | Storage gate protection | Nov 27, 2016 | Issued |
Array
(
[id] => 14707081
[patent_doc_number] => 10381300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Semiconductor device package including filling mold via
[patent_app_type] => utility
[patent_app_number] => 15/362548
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 5297
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362548
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362548 | Semiconductor device package including filling mold via | Nov 27, 2016 | Issued |
Array
(
[id] => 14011585
[patent_doc_number] => 10224268
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-03-05
[patent_title] => Enhanced thermal transfer in a semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 15/362504
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8374
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362504
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362504 | Enhanced thermal transfer in a semiconductor structure | Nov 27, 2016 | Issued |
Array
(
[id] => 12294369
[patent_doc_number] => 09935144
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-04-03
[patent_title] => System-in-package image sensor
[patent_app_type] => utility
[patent_app_number] => 15/362408
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 2498
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362408
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362408 | System-in-package image sensor | Nov 27, 2016 | Issued |
Array
(
[id] => 13653331
[patent_doc_number] => 09852986
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-12-26
[patent_title] => Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
[patent_app_type] => utility
[patent_app_number] => 15/362035
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 6807
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362035
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362035 | Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit | Nov 27, 2016 | Issued |
Array
(
[id] => 12026990
[patent_doc_number] => 20170317089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-02
[patent_title] => 'METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS'
[patent_app_type] => utility
[patent_app_number] => 15/362002
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 12458
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362002
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362002 | Method of manufacturing fins and semiconductor device which includes fins | Nov 27, 2016 | Issued |
Array
(
[id] => 13174005
[patent_doc_number] => 10103125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Chip package structure and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 15/362690
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 7573
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362690
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362690 | Chip package structure and method for forming the same | Nov 27, 2016 | Issued |
Array
(
[id] => 12195587
[patent_doc_number] => 09899324
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-02-20
[patent_title] => 'Structure and method of conductive bus bar for resistive seed substrate plating'
[patent_app_type] => utility
[patent_app_number] => 15/362499
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 5310
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362499
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362499 | Structure and method of conductive bus bar for resistive seed substrate plating | Nov 27, 2016 | Issued |
Array
(
[id] => 11746655
[patent_doc_number] => 20170200728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-13
[patent_title] => 'METHOD OF MANUFACTURING AN EEPROM DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/362551
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6141
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362551
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362551 | Method of manufacturing an EEPROM device | Nov 27, 2016 | Issued |
Array
(
[id] => 11737468
[patent_doc_number] => 09702042
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-07-11
[patent_title] => 'Method and apparatus for single chamber treatment'
[patent_app_type] => utility
[patent_app_number] => 15/352917
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1363
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352917
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/352917 | Method and apparatus for single chamber treatment | Nov 15, 2016 | Issued |