
Nathan W. Ha
Examiner (ID: 14314)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 2125 |
| Issued Applications | 1816 |
| Pending Applications | 114 |
| Abandoned Applications | 221 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12102257
[patent_doc_number] => 09859357
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-02
[patent_title] => 'Magnetic inductor stacks with multilayer isolation layers'
[patent_app_type] => utility
[patent_app_number] => 15/209803
[patent_app_country] => US
[patent_app_date] => 2016-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2972
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209803
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209803 | Magnetic inductor stacks with multilayer isolation layers | Jul 13, 2016 | Issued |
Array
(
[id] => 11524571
[patent_doc_number] => 09607982
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-28
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 15/209771
[patent_app_country] => US
[patent_app_date] => 2016-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2770
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209771
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209771 | Semiconductor device and method for fabricating the same | Jul 13, 2016 | Issued |
Array
(
[id] => 11446421
[patent_doc_number] => 20170047442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/208936
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11942
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208936
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208936 | Semiconductor device | Jul 12, 2016 | Issued |
Array
(
[id] => 11397967
[patent_doc_number] => 20170018504
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-19
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING STRUCTURE FOR IMPROVING VOLTAGE DROP AND DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/208639
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6378
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208639
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208639 | Semiconductor device having structure for improving voltage drop and device including the same | Jul 12, 2016 | Issued |
Array
(
[id] => 12192610
[patent_doc_number] => 09896329
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Integrated semiconductor device and manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 15/208975
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 8056
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208975
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208975 | Integrated semiconductor device and manufacturing method | Jul 12, 2016 | Issued |
Array
(
[id] => 11424888
[patent_doc_number] => 20170033034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-02
[patent_title] => 'ELECTRONIC DEVICE AND PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 15/208827
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2536
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208827
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208827 | ELECTRONIC DEVICE AND PACKAGE | Jul 12, 2016 | Abandoned |
Array
(
[id] => 12141165
[patent_doc_number] => 20180019249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'INTEGRATED CIRCUITS WITH PROGRAMMABLE MEMORY AND METHODS FOR PRODUCING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/209102
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4381
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209102
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209102 | Integrated circuits with programmable memory and methods for producing the same | Jul 12, 2016 | Issued |
Array
(
[id] => 12174910
[patent_doc_number] => 09893058
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Method of manufacturing a semiconductor device having reduced on-state resistance and structure'
[patent_app_type] => utility
[patent_app_number] => 15/208794
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 6733
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208794
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208794 | Method of manufacturing a semiconductor device having reduced on-state resistance and structure | Jul 12, 2016 | Issued |
Array
(
[id] => 12115023
[patent_doc_number] => 09871019
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Flipped die stack assemblies with leadframe interconnects'
[patent_app_type] => utility
[patent_app_number] => 15/209034
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 5340
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209034
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209034 | Flipped die stack assemblies with leadframe interconnects | Jul 12, 2016 | Issued |
Array
(
[id] => 11911387
[patent_doc_number] => 09780209
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-03
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 15/208830
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4690
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208830
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208830 | Semiconductor device and manufacturing method thereof | Jul 12, 2016 | Issued |
Array
(
[id] => 11459976
[patent_doc_number] => 20170053882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA'
[patent_app_type] => utility
[patent_app_number] => 15/209298
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 15349
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209298
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209298 | Electronic device having a redistribution area | Jul 12, 2016 | Issued |
Array
(
[id] => 11551587
[patent_doc_number] => 09620443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Semiconductor component and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 15/208703
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 55
[patent_no_of_words] => 12135
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208703
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208703 | Semiconductor component and method of manufacture | Jul 12, 2016 | Issued |
Array
(
[id] => 13640875
[patent_doc_number] => 09847398
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-12-19
[patent_title] => Semiconductor device with gate structure having dielectric layer on one side and contact plug on the other side
[patent_app_type] => utility
[patent_app_number] => 15/208616
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2555
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208616
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/208616 | Semiconductor device with gate structure having dielectric layer on one side and contact plug on the other side | Jul 12, 2016 | Issued |
Array
(
[id] => 12175041
[patent_doc_number] => 09893189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Method for reducing contact resistance in semiconductor structures'
[patent_app_type] => utility
[patent_app_number] => 15/209224
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9472
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209224
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209224 | Method for reducing contact resistance in semiconductor structures | Jul 12, 2016 | Issued |
Array
(
[id] => 11862142
[patent_doc_number] => 09741837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Bidirectional insulated gate bipolar transistor'
[patent_app_type] => utility
[patent_app_number] => 15/209745
[patent_app_country] => US
[patent_app_date] => 2016-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4621
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209745
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/209745 | Bidirectional insulated gate bipolar transistor | Jul 12, 2016 | Issued |
Array
(
[id] => 14414195
[patent_doc_number] => 20190172941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN
[patent_app_type] => utility
[patent_app_number] => 16/304620
[patent_app_country] => US
[patent_app_date] => 2016-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16304620
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/304620 | Semiconductor device with released source and drain | Jul 1, 2016 | Issued |
Array
(
[id] => 16911442
[patent_doc_number] => 11043492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-22
[patent_title] => Self-aligned gate edge trigate and finFET devices
[patent_app_type] => utility
[patent_app_number] => 16/098084
[patent_app_country] => US
[patent_app_date] => 2016-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 32
[patent_no_of_words] => 11487
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16098084
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/098084 | Self-aligned gate edge trigate and finFET devices | Jun 30, 2016 | Issued |
Array
(
[id] => 16536731
[patent_doc_number] => 10879346
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Capacitor including multilayer dielectric stack
[patent_app_type] => utility
[patent_app_number] => 16/303821
[patent_app_country] => US
[patent_app_date] => 2016-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303821
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/303821 | Capacitor including multilayer dielectric stack | Jun 30, 2016 | Issued |
Array
(
[id] => 11110828
[patent_doc_number] => 20160307798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'RELIABLE PACKAGING AND INTERCONNECT STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 15/195641
[patent_app_country] => US
[patent_app_date] => 2016-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4629
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195641
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/195641 | Reliable packaging and interconnect structures | Jun 27, 2016 | Issued |
Array
(
[id] => 11111553
[patent_doc_number] => 20160308523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'POWER CIRCUIT AND POWER MODULE'
[patent_app_type] => utility
[patent_app_number] => 15/192677
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 19958
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192677
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192677 | Power circuit and power module using MISFET having control circuit disposed between gate and source | Jun 23, 2016 | Issued |