
Nathan W. Ha
Examiner (ID: 14314)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 2125 |
| Issued Applications | 1816 |
| Pending Applications | 114 |
| Abandoned Applications | 221 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 11111035
[patent_doc_number] => 20160308005
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[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE'
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Array
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[patent_issue_date] => 2017-01-31
[patent_title] => 'FinFET conformal junction and abrupt junction with reduced damage method and device'
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[patent_title] => 'Tipless transistors, short-tip transistors, and methods and circuits therefor'
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Array
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[patent_title] => 'METHOD AND APPARATUS FOR USING UNIVERSAL CAVITY WAFER IN WAFER LEVEL PACKAGING'
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Array
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[patent_title] => FORMING INSULATOR FIN STRUCTURE IN ISOLATION REGION TO SUPPORT GATE STRUCTURES
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Array
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[patent_doc_number] => 20170358677
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[patent_title] => STRAINED SILICON COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INCLUDING A SILICON CONTAINING TENSILE N-TYPE FIN FIELD EFFECT TRANSISTOR AND SILICON CONTAINING COMPRESSIVE P-TYPE FIN FIELD EFFECT TRANSISTOR FORMED USING A DUAL RELAXED SUBSTRATE
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/178010 | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate | Jun 8, 2016 | Issued |
Array
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[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
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[patent_app_number] => 15/177897
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[patent_title] => 'Semiconductor device and manufacturing method thereof'
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Array
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[patent_title] => Atomic layer deposition methods and structures thereof
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/177921 | Semiconductor device having electrode pads arranged between groups of external electrodes | Jun 8, 2016 | Issued |
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