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Nathan W. Ha

Examiner (ID: 14314)

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
2125
Issued Applications
1816
Pending Applications
114
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11111035 [patent_doc_number] => 20160308005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE' [patent_app_type] => utility [patent_app_number] => 15/189079 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/189079
FinFET conformal junction and high epi surface dopant concentration method and device Jun 21, 2016 Issued
Array ( [id] => 11411859 [patent_doc_number] => 09559176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'FinFET conformal junction and abrupt junction with reduced damage method and device' [patent_app_type] => utility [patent_app_number] => 15/180312 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15180312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/180312
FinFET conformal junction and abrupt junction with reduced damage method and device Jun 12, 2016 Issued
Array ( [id] => 11466843 [patent_doc_number] => 09583484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Tipless transistors, short-tip transistors, and methods and circuits therefor' [patent_app_type] => utility [patent_app_number] => 15/179370 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 8174 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15179370 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/179370
Tipless transistors, short-tip transistors, and methods and circuits therefor Jun 9, 2016 Issued
Array ( [id] => 11339565 [patent_doc_number] => 20160365321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'METHOD AND APPARATUS FOR USING UNIVERSAL CAVITY WAFER IN WAFER LEVEL PACKAGING' [patent_app_type] => utility [patent_app_number] => 15/177723 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4742 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177723
Method and apparatus for using universal cavity wafer in wafer level packaging Jun 8, 2016 Issued
Array ( [id] => 13695087 [patent_doc_number] => 20170358498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => FORMING INSULATOR FIN STRUCTURE IN ISOLATION REGION TO SUPPORT GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/177917 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177917 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177917
Forming insulator fin structure in isolation region to support gate structures Jun 8, 2016 Issued
Array ( [id] => 13695445 [patent_doc_number] => 20170358677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => STRAINED SILICON COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INCLUDING A SILICON CONTAINING TENSILE N-TYPE FIN FIELD EFFECT TRANSISTOR AND SILICON CONTAINING COMPRESSIVE P-TYPE FIN FIELD EFFECT TRANSISTOR FORMED USING A DUAL RELAXED SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/178010 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178010
Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate Jun 8, 2016 Issued
Array ( [id] => 11824906 [patent_doc_number] => 20170213843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/177897 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9759 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177897 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177897
Semiconductor device and method of manufacturing the same Jun 8, 2016 Issued
Array ( [id] => 12147611 [patent_doc_number] => 09881870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/178115 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178115
Semiconductor device and manufacturing method thereof Jun 8, 2016 Issued
Array ( [id] => 13653301 [patent_doc_number] => 09852971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Interposer, semiconductor package structure, and semiconductor process [patent_app_type] => utility [patent_app_number] => 15/178066 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 9018 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178066 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178066
Interposer, semiconductor package structure, and semiconductor process Jun 8, 2016 Issued
Array ( [id] => 12417234 [patent_doc_number] => 09972694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Atomic layer deposition methods and structures thereof [patent_app_type] => utility [patent_app_number] => 15/178150 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178150
Atomic layer deposition methods and structures thereof Jun 8, 2016 Issued
Array ( [id] => 11385980 [patent_doc_number] => 20170012036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'Electrostatic Discharge Protection Device Comprising a Silicon Controlled Rectifier' [patent_app_type] => utility [patent_app_number] => 15/177858 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6567 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177858
Electrostatic discharge protection device comprising a silicon controlled rectifier Jun 8, 2016 Issued
Array ( [id] => 11911165 [patent_doc_number] => 09779984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of forming trenches with different depths' [patent_app_type] => utility [patent_app_number] => 15/178229 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178229
Method of forming trenches with different depths Jun 8, 2016 Issued
Array ( [id] => 11818061 [patent_doc_number] => 09722024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Formation of semiconductor structures employing selective removal of fins' [patent_app_type] => utility [patent_app_number] => 15/178134 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2984 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178134
Formation of semiconductor structures employing selective removal of fins Jun 8, 2016 Issued
Array ( [id] => 12040452 [patent_doc_number] => 09818687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Semiconductor module and method of manufacturing semiconductor module' [patent_app_type] => utility [patent_app_number] => 15/177658 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6989 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177658 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177658
Semiconductor module and method of manufacturing semiconductor module Jun 8, 2016 Issued
Array ( [id] => 11489381 [patent_doc_number] => 09595455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-14 [patent_title] => 'Integrated circuit module with filled contact gaps' [patent_app_type] => utility [patent_app_number] => 15/178329 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178329
Integrated circuit module with filled contact gaps Jun 8, 2016 Issued
Array ( [id] => 12969157 [patent_doc_number] => 09875959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Forming a stacked capacitor [patent_app_type] => utility [patent_app_number] => 15/178245 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4145 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178245
Forming a stacked capacitor Jun 8, 2016 Issued
Array ( [id] => 11096541 [patent_doc_number] => 20160293510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES' [patent_app_type] => utility [patent_app_number] => 15/177921 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4088 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177921
Semiconductor device having electrode pads arranged between groups of external electrodes Jun 8, 2016 Issued
Array ( [id] => 13695435 [patent_doc_number] => 20170358672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => SELF-ALIGNED SHALLOW TRENCH ISOLATION AND DOPING FOR VERTICAL FIN TRANSISTORS [patent_app_type] => utility [patent_app_number] => 15/178193 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178193 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178193
Self-aligned shallow trench isolation and doping for vertical fin transistors Jun 8, 2016 Issued
Array ( [id] => 11337882 [patent_doc_number] => 20160363637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'MAGNETIC FIELD MEASURING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/177818 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2856 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177818 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177818
Magnetic field measuring device Jun 8, 2016 Issued
Array ( [id] => 11483377 [patent_doc_number] => 09589932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Interconnect structures for wafer level package and methods of forming same' [patent_app_type] => utility [patent_app_number] => 15/174606 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174606
Interconnect structures for wafer level package and methods of forming same Jun 5, 2016 Issued
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