Nathan W. Ha

Array ( [id] => 8390769 [patent_doc_number] => 20120228611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE' [patent_app_type] => utility [patent_app_number] => 13/042902 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9516 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6083381 [patent_doc_number] => 20110215299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND DOPANT DIFFUSION RETARDING IMPLANTS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/042826 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4667 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20110215299.pdf [firstpage_image] =>[orig_patent_app_number] => 13042826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8543947 [patent_doc_number] => 08319241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Light emitting device, light emitting device package, and lighting system' [patent_app_type] => utility [patent_app_number] => 13/042884 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8340577 [patent_doc_number] => 08242503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Multi-gate thin film transistor device' [patent_app_type] => utility [patent_app_number] => 13/042861 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9245843 [patent_doc_number] => 08610126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Flat panel display device with simplified efficient structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/042986 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3998 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7480770 [patent_doc_number] => 20110233660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/042801 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233660.pdf [firstpage_image] =>[orig_patent_app_number] => 13042801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6083794 [patent_doc_number] => 20110215444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES' [patent_app_type] => utility [patent_app_number] => 13/042855 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8366 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20110215444.pdf [firstpage_image] =>[orig_patent_app_number] => 13042855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8390791 [patent_doc_number] => 20120228629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors' [patent_app_type] => utility [patent_app_number] => 13/043295 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11439 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13043295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7699447 [patent_doc_number] => 20110227143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'INTEGRATED CIRCUIT DEVICES INCLUDING COMPLEX DIELECTRIC LAYERS AND RELATED FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 13/042871 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8627 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227143.pdf [firstpage_image] =>[orig_patent_app_number] => 13042871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8299132 [patent_doc_number] => 20120181698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'FORMING THROUGH-SILICON-VIAS FOR MULTI-WAFER INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/008845 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13008845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8726027 [patent_doc_number] => 08405150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Contoured insulator layer of silicon-on-insulator wafers and process of manufacture' [patent_app_type] => utility [patent_app_number] => 12/987232 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5263 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4604704 [patent_doc_number] => 07985684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-26 [patent_title] => 'Actuating transistor including reduced channel length' [patent_app_type] => utility [patent_app_number] => 12/986199 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5842 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/985/07985684.pdf [firstpage_image] =>[orig_patent_app_number] => 12986199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6038978 [patent_doc_number] => 20110092027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE HAVING A CASTELLATED HEATSPREADER' [patent_app_type] => utility [patent_app_number] => 12/975310 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4325 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20110092027.pdf [firstpage_image] =>[orig_patent_app_number] => 12975310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6120840 [patent_doc_number] => 20110084359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/968534 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7551 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084359.pdf [firstpage_image] =>[orig_patent_app_number] => 12968534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6082419 [patent_doc_number] => 20110143662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND COMMUNICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/926709 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5980 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20110143662.pdf [firstpage_image] =>[orig_patent_app_number] => 12926709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6114686 [patent_doc_number] => 20110074047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die' [patent_app_type] => utility [patent_app_number] => 12/959709 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18520 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074047.pdf [firstpage_image] =>[orig_patent_app_number] => 12959709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6114686 [patent_doc_number] => 20110074047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die' [patent_app_type] => utility [patent_app_number] => 12/959709 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18520 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074047.pdf [firstpage_image] =>[orig_patent_app_number] => 12959709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4450965 [patent_doc_number] => 07964288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/947275 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 69 [patent_no_of_words] => 14064 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964288.pdf [firstpage_image] =>[orig_patent_app_number] => 12947275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6067896 [patent_doc_number] => 20110042833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/939642 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3827 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20110042833.pdf [firstpage_image] =>[orig_patent_app_number] => 12939642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8166470 [patent_doc_number] => 20120104611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'SEMICONDUCTOR STRUCTURE WITH INSULATED THROUGH SILICON VIA' [patent_app_type] => utility [patent_app_number] => 13/122957 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9444 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104611.pdf [firstpage_image] =>[orig_patent_app_number] => 13122957 [rel_patent_id] =>[rel_patent_doc_number] =>)