Search

Nathaniel Herzfeld

Examiner (ID: 14578, Phone: (571)272-5899 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
626
Issued Applications
427
Pending Applications
1
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20635799 [patent_doc_number] => 12596673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Systems and methods for implementing directional operand broadcast and multiply-accumulate execution using a configurable patch mesh in a multi-core processing array of an integrated circuit [patent_app_type] => utility [patent_app_number] => 19/273567 [patent_app_country] => US [patent_app_date] => 2025-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19273567 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/273567
Systems and methods for implementing directional operand broadcast and multiply-accumulate execution using a configurable patch mesh in a multi-core processing array of an integrated circuit Jul 17, 2025 Issued
Array ( [id] => 20095024 [patent_doc_number] => 20250224960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => TASK EXECUTION METHOD FOR LARGE MODEL, ELECTRONIC DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/089853 [patent_app_country] => US [patent_app_date] => 2025-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19089853 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/089853
TASK EXECUTION METHOD FOR LARGE MODEL, ELECTRONIC DEVICE, AND STORAGE MEDIUM Mar 24, 2025 Pending
Array ( [id] => 20234328 [patent_doc_number] => 20250291647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => STARVATION AVOIDANCE IN AN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 19/077136 [patent_app_country] => US [patent_app_date] => 2025-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19077136 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/077136
STARVATION AVOIDANCE IN AN OUT-OF-ORDER PROCESSOR Mar 11, 2025 Pending
Array ( [id] => 20181130 [patent_doc_number] => 20250265088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES [patent_app_type] => utility [patent_app_number] => 19/053495 [patent_app_country] => US [patent_app_date] => 2025-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19053495 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/053495
COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES Feb 13, 2025 Pending
Array ( [id] => 20297705 [patent_doc_number] => 20250322948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => EFFICIENT COMPRESSION INSTRUCTION HANDLING IN A PROCESSING PIPELINE [patent_app_type] => utility [patent_app_number] => 19/035792 [patent_app_country] => US [patent_app_date] => 2025-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19035792 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/035792
EFFICIENT COMPRESSION INSTRUCTION HANDLING IN A PROCESSING PIPELINE Jan 22, 2025 Pending
Array ( [id] => 20152099 [patent_doc_number] => 20250251937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => CIRCUIT AND METHOD FOR DYNAMIC REGISTER ALLOCATION FOR A GRAPHICS PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 19/035024 [patent_app_country] => US [patent_app_date] => 2025-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19035024 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/035024
CIRCUIT AND METHOD FOR DYNAMIC REGISTER ALLOCATION FOR A GRAPHICS PROCESSING UNIT Jan 22, 2025 Pending
Array ( [id] => 20310721 [patent_doc_number] => 20250328350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline [patent_app_type] => utility [patent_app_number] => 19/018392 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018392 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018392
Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline Jan 12, 2025 Pending
Array ( [id] => 19992588 [patent_doc_number] => 20250130810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SHADER INPUT DATA PROCESSING METHOD AND GRAPHICS PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 19/001115 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001115 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001115
SHADER INPUT DATA PROCESSING METHOD AND GRAPHICS PROCESSING APPARATUS Dec 23, 2024 Pending
Array ( [id] => 19992584 [patent_doc_number] => 20250130806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Implicit Global Pointer Relative Addressing for Global Memory Access [patent_app_type] => utility [patent_app_number] => 18/990578 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18990578 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/990578
Implicit Global Pointer Relative Addressing for Global Memory Access Dec 19, 2024 Pending
Array ( [id] => 19849028 [patent_doc_number] => 20250094379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => DATA-FLOW-DRIVEN RECONFIGURABLE PROCESSOR CHIP AND RECONFIGURABLE PROCESSOR CLUSTER [patent_app_type] => utility [patent_app_number] => 18/971323 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971323
DATA-FLOW-DRIVEN RECONFIGURABLE PROCESSOR CHIP AND RECONFIGURABLE PROCESSOR CLUSTER Dec 5, 2024 Pending
Array ( [id] => 19865394 [patent_doc_number] => 20250104180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/967172 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967172
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY Dec 2, 2024 Pending
Array ( [id] => 20027892 [patent_doc_number] => 20250166114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/967123 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967123
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY Dec 2, 2024 Pending
Array ( [id] => 20380426 [patent_doc_number] => 20250362919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => METHOD FOR PROCESSING INSTRUCTION, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/952665 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952665
METHOD FOR PROCESSING INSTRUCTION, DEVICE, AND STORAGE MEDIUM Nov 18, 2024 Pending
Array ( [id] => 19725754 [patent_doc_number] => 20250028505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => ACCELERATING 2D CONVOLUTIONAL LAYER MAPPING ON A DOT PRODUCT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/908555 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908555
ACCELERATING 2D CONVOLUTIONAL LAYER MAPPING ON A DOT PRODUCT ARCHITECTURE Oct 6, 2024 Pending
Array ( [id] => 19725814 [patent_doc_number] => 20250028565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/906648 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906648
SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS Oct 3, 2024 Pending
Array ( [id] => 20758160 [patent_doc_number] => 12650931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Atomic update instructions with bit masking [patent_app_type] => utility [patent_app_number] => 18/898584 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898584
Atomic update instructions with bit masking Sep 25, 2024 Issued
Array ( [id] => 19864763 [patent_doc_number] => 20250103549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, PROCESSOR, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/896789 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896789
Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor Sep 24, 2024 Issued
Array ( [id] => 20616709 [patent_doc_number] => 20260086805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => LOOP DETECTOR AND PREDICTOR [patent_app_type] => utility [patent_app_number] => 18/891608 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891608
LOOP DETECTOR AND PREDICTOR Sep 19, 2024 Pending
Array ( [id] => 20570489 [patent_doc_number] => 20260064413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => STORAGE INSTRUCTION FOR MATRIX MULTIPLY-ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/819931 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 72625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819931
STORAGE INSTRUCTION FOR MATRIX MULTIPLY-ACCUMULATE OPERATIONS Aug 28, 2024 Pending
Array ( [id] => 20570500 [patent_doc_number] => 20260064424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => SELECTING A CANDIDATE CONSUMER INSTRUCTION BASED ON AN OBSERVED INSTRUCTION HAVING A DEPENDENCY MARKED SOURCE OPERAND FROM PRODUCER DATA OF A PRODUCER INSTRUCTION [patent_app_type] => utility [patent_app_number] => 18/817355 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817355
Selecting a candidate consumer instruction based on an observed instruction having a dependency marked source operand from producer data of a producer instruction Aug 27, 2024 Issued
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