Search

Nathaniel Herzfeld

Examiner (ID: 14578, Phone: (571)272-5899 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
626
Issued Applications
427
Pending Applications
1
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17084059 [patent_doc_number] => 20210279065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => LIGHTWEIGHT MEMORY ORDERING PRIMITIVES [patent_app_type] => utility [patent_app_number] => 16/808346 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808346
LIGHTWEIGHT MEMORY ORDERING PRIMITIVES Mar 2, 2020 Abandoned
Array ( [id] => 17069264 [patent_doc_number] => 20210271480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => DELIVERING IMMEDIATE VALUES BY USING PROGRAM COUNTER (PC)-RELATIVE LOAD INSTRUCTIONS TO FETCH LITERAL DATA IN PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/806342 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806342
Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices Mar 1, 2020 Issued
Array ( [id] => 16017689 [patent_doc_number] => 20200183688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => PACKED DATA OPERATION MASK SHIFT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/788285 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788285
PACKED DATA OPERATION MASK SHIFT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Feb 10, 2020 Abandoned
Array ( [id] => 16416479 [patent_doc_number] => 10824370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Systems and methods for implementing random access memory in a flow-based machine perception and dense algorithm integrated circuit based on computing and coalescing of indices [patent_app_type] => utility [patent_app_number] => 16/778578 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12069 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/778578
Systems and methods for implementing random access memory in a flow-based machine perception and dense algorithm integrated circuit based on computing and coalescing of indices Jan 30, 2020 Issued
Array ( [id] => 15966815 [patent_doc_number] => 20200167159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => PROCESSOR TESTING [patent_app_type] => utility [patent_app_number] => 16/776041 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776041
Processor testing using pairs of counter incrementing and branch instructions Jan 28, 2020 Issued
Array ( [id] => 16592477 [patent_doc_number] => 10901739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Systems and methods for controlling machine operations using stack entries comprising instruction configuration parameters [patent_app_type] => utility [patent_app_number] => 16/747242 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5146 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747242
Systems and methods for controlling machine operations using stack entries comprising instruction configuration parameters Jan 19, 2020 Issued
Array ( [id] => 16934649 [patent_doc_number] => 20210200538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => DUAL WRITE MICRO-OP QUEUE [patent_app_type] => utility [patent_app_number] => 16/729362 [patent_app_country] => US [patent_app_date] => 2019-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729362
DUAL WRITE MICRO-OP QUEUE Dec 27, 2019 Abandoned
Array ( [id] => 16934822 [patent_doc_number] => 20210200711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => System and Method for Configurable Systolic Array with Partial Read/Write [patent_app_type] => utility [patent_app_number] => 16/729381 [patent_app_country] => US [patent_app_date] => 2019-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729381
System and Method for Configurable Systolic Array with Partial Read/Write Dec 27, 2019 Abandoned
Array ( [id] => 18235211 [patent_doc_number] => 11599770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Methods and devices for programming a state machine engine [patent_app_type] => utility [patent_app_number] => 16/715755 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12045 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715755
Methods and devices for programming a state machine engine Dec 15, 2019 Issued
Array ( [id] => 18592446 [patent_doc_number] => 11741349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Performing matrix-vector multiply operations for neural networks on electronic devices [patent_app_type] => utility [patent_app_number] => 16/670140 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670140
Performing matrix-vector multiply operations for neural networks on electronic devices Oct 30, 2019 Issued
Array ( [id] => 16894947 [patent_doc_number] => 11036500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Technique for processing a sequence of atomic add with carry instructions when a data value is not present in a cache [patent_app_type] => utility [patent_app_number] => 16/661196 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661196
Technique for processing a sequence of atomic add with carry instructions when a data value is not present in a cache Oct 22, 2019 Issued
Array ( [id] => 17861575 [patent_doc_number] => 11442731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Data processing systems including an intermediate buffer with controlled data value eviction [patent_app_type] => utility [patent_app_number] => 16/656385 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 18535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656385
Data processing systems including an intermediate buffer with controlled data value eviction Oct 16, 2019 Issued
Array ( [id] => 17492161 [patent_doc_number] => 11281464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Method and apparatus to sort a vector for a bitonic sorting algorithm [patent_app_type] => utility [patent_app_number] => 16/589133 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 55 [patent_no_of_words] => 32264 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589133
Method and apparatus to sort a vector for a bitonic sorting algorithm Sep 29, 2019 Issued
Array ( [id] => 17252848 [patent_doc_number] => 11188337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Micro-architecture designs and methods for eager execution and fetching of instructions [patent_app_type] => utility [patent_app_number] => 16/588692 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588692
Micro-architecture designs and methods for eager execution and fetching of instructions Sep 29, 2019 Issued
Array ( [id] => 16729730 [patent_doc_number] => 20210096877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => COLLAPSING BUBBLES IN A PROCESSING UNIT PIPELINE [patent_app_type] => utility [patent_app_number] => 16/583969 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583969
COLLAPSING BUBBLES IN A PROCESSING UNIT PIPELINE Sep 25, 2019 Abandoned
Array ( [id] => 18826890 [patent_doc_number] => 11842169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-12 [patent_title] => Systolic multiply delayed accumulate processor architecture [patent_app_type] => utility [patent_app_number] => 16/582918 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582918 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582918
Systolic multiply delayed accumulate processor architecture Sep 24, 2019 Issued
Array ( [id] => 17763380 [patent_doc_number] => 20220236992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => RISC-V BRANCH PREDICTION METHOD, DEVICE, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/613661 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/613661
RISC-V BRANCH PREDICTION METHOD, DEVICE, ELECTRONIC DEVICE AND STORAGE MEDIUM Aug 29, 2019 Abandoned
Array ( [id] => 15530679 [patent_doc_number] => 20200057645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => SYSTEM AND METHOD FOR LOCATION AWARE PROCESSING [patent_app_type] => utility [patent_app_number] => 16/540328 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540328
SYSTEM AND METHOD FOR LOCATION AWARE PROCESSING Aug 13, 2019 Abandoned
Array ( [id] => 15151789 [patent_doc_number] => 20190354372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => METHOD FOR MAINTAINING A BRANCH PREDICTION HISTORY TABLE [patent_app_type] => utility [patent_app_number] => 16/527244 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527244
Method for maintaining a branch prediction history table Jul 30, 2019 Issued
Array ( [id] => 17454785 [patent_doc_number] => 11269644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => System and method for implementing strong load ordering in a processor using a circular ordering ring [patent_app_type] => utility [patent_app_number] => 16/525519 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8062 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525519 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525519
System and method for implementing strong load ordering in a processor using a circular ordering ring Jul 28, 2019 Issued
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