Search

Nathaniel Herzfeld

Examiner (ID: 14578, Phone: (571)272-5899 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
626
Issued Applications
427
Pending Applications
1
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14314193 [patent_doc_number] => 20190146800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => MIXED INFERENCE USING LOW AND HIGH PRECISION [patent_app_type] => utility [patent_app_number] => 16/227645 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227645
Compute unit having independent data paths Dec 19, 2018 Issued
Array ( [id] => 16017705 [patent_doc_number] => 20200183696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A FRONTING LOAD [patent_app_type] => utility [patent_app_number] => 16/216659 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216659
Synchronized access to data in shared memory by protecting the load target address of a fronting load Dec 10, 2018 Issued
Array ( [id] => 16574119 [patent_doc_number] => 10896042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Vector population count determination via comparison iterations in memory [patent_app_type] => utility [patent_app_number] => 16/207786 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 29865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207786
Vector population count determination via comparison iterations in memory Dec 2, 2018 Issued
Array ( [id] => 15772863 [patent_doc_number] => 20200117449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Accelerated Access to Computations Results Generated from Data Stored in Memory Devices [patent_app_type] => utility [patent_app_number] => 16/158558 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158558 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/158558
Accelerated Access to Computations Results Generated from Data Stored in Memory Devices Oct 11, 2018 Abandoned
Array ( [id] => 16894957 [patent_doc_number] => 11036510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Processing merging predicated instruction with timing permitting previous value of destination register to be unavailable when the merging predicated instruction is at a given pipeline stage at which a processing result is determined [patent_app_type] => utility [patent_app_number] => 16/157400 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8971 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157400
Processing merging predicated instruction with timing permitting previous value of destination register to be unavailable when the merging predicated instruction is at a given pipeline stage at which a processing result is determined Oct 10, 2018 Issued
Array ( [id] => 15772873 [patent_doc_number] => 20200117454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => VECTOR REGISTERS IMPLEMENTED IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/156808 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156808
Vector registers implemented in memory Oct 9, 2018 Issued
Array ( [id] => 14657495 [patent_doc_number] => 20190235876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => METHODS FOR SCHEDULING MICRO-INSTRUCTIONS AND APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/149706 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149706 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149706
Scheduling that determines whether to remove a dependent micro-instruction from a reservation station queue based on determining cache hit/miss status of one ore more load micro-instructions once a count reaches a predetermined value Oct 1, 2018 Issued
Array ( [id] => 16494285 [patent_doc_number] => 10860327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Methods for scheduling that determine whether to remove a dependent micro-instruction from a reservation station queue based on determining a cache hit/miss status of a load micro-instruction once a count reaches a predetermined value and an apparatus using the same [patent_app_type] => utility [patent_app_number] => 16/149681 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149681
Methods for scheduling that determine whether to remove a dependent micro-instruction from a reservation station queue based on determining a cache hit/miss status of a load micro-instruction once a count reaches a predetermined value and an apparatus using the same Oct 1, 2018 Issued
Array ( [id] => 17031439 [patent_doc_number] => 11093250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Apparatus and method for gang invariant operation optimizations using dynamic evaluation [patent_app_type] => utility [patent_app_number] => 16/147694 [patent_app_country] => US [patent_app_date] => 2018-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 46 [patent_no_of_words] => 25518 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147694
Apparatus and method for gang invariant operation optimizations using dynamic evaluation Sep 28, 2018 Issued
Array ( [id] => 14135559 [patent_doc_number] => 20190102169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => EFFECTIVE DETERMINATION OF PROCESSOR PAIRS FOR TRANSFERRING DATA PROCESSED IN PARALLEL [patent_app_type] => utility [patent_app_number] => 16/137618 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137618
EFFECTIVE DETERMINATION OF PROCESSOR PAIRS FOR TRANSFERRING DATA PROCESSED IN PARALLEL Sep 20, 2018 Abandoned
Array ( [id] => 14022687 [patent_doc_number] => 20190073337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => APPARATUSES CAPABLE OF PROVIDING COMPOSITE INSTRUCTIONS IN THE INSTRUCTION SET ARCHITECTURE OF A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/120645 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/120645
APPARATUSES CAPABLE OF PROVIDING COMPOSITE INSTRUCTIONS IN THE INSTRUCTION SET ARCHITECTURE OF A PROCESSOR Sep 3, 2018 Abandoned
Array ( [id] => 19732878 [patent_doc_number] => 12210876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Implicit global pointer relative addressing for global memory access [patent_app_type] => utility [patent_app_number] => 16/119291 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22050 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119291
Implicit global pointer relative addressing for global memory access Aug 30, 2018 Issued
Array ( [id] => 13992083 [patent_doc_number] => 20190065199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SAVING AND RESTORING NON-CONTIGUOUS BLOCKS OF PRESERVED REGISTERS [patent_app_type] => utility [patent_app_number] => 16/119347 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119347
SAVING AND RESTORING NON-CONTIGUOUS BLOCKS OF PRESERVED REGISTERS Aug 30, 2018 Abandoned
Array ( [id] => 14282037 [patent_doc_number] => 20190138303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/110298 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/110298
APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION Aug 22, 2018 Abandoned
Array ( [id] => 15439925 [patent_doc_number] => 20200034146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A FRONTING LOAD [patent_app_type] => utility [patent_app_number] => 16/048884 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048884
SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A FRONTING LOAD Jul 29, 2018 Abandoned
Array ( [id] => 16355169 [patent_doc_number] => 10795679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Memory access instructions that include permission values for additional protection [patent_app_type] => utility [patent_app_number] => 16/002839 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11258 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16002839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/002839
Memory access instructions that include permission values for additional protection Jun 6, 2018 Issued
Array ( [id] => 19719369 [patent_doc_number] => 12204908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Storing incidental branch predictions to reduce latency of misprediction recovery [patent_app_type] => utility [patent_app_number] => 15/997344 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/997344
Storing incidental branch predictions to reduce latency of misprediction recovery Jun 3, 2018 Issued
Array ( [id] => 15820531 [patent_doc_number] => 10635445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Handling modifications to permitted program counter ranges in a data processing apparatus [patent_app_type] => utility [patent_app_number] => 15/991220 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991220
Handling modifications to permitted program counter ranges in a data processing apparatus May 28, 2018 Issued
Array ( [id] => 15182233 [patent_doc_number] => 20190361708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => EMBEDDED SCHEDULING OF HARDWARE RESOURCES FOR HARDWARE ACCELERATION [patent_app_type] => utility [patent_app_number] => 15/988900 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988900 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988900
Embedded scheduling of hardware resources for hardware acceleration May 23, 2018 Issued
Array ( [id] => 13611031 [patent_doc_number] => 20180357065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => PROGRAMMABLE INSTRUCTION BUFFERING [patent_app_type] => utility [patent_app_number] => 15/974769 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974769
Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory address May 8, 2018 Issued
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