Search

Nathaniel Herzfeld

Examiner (ID: 14578, Phone: (571)272-5899 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
626
Issued Applications
427
Pending Applications
1
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15516771 [patent_doc_number] => 10564971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Method and apparatus for processing macro instruction using one or more shared operators [patent_app_type] => utility [patent_app_number] => 15/535304 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3814 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535304
Method and apparatus for processing macro instruction using one or more shared operators Oct 14, 2015 Issued
Array ( [id] => 16636814 [patent_doc_number] => 10915323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Method and device for processing an instruction having multi-instruction data including configurably concatenating portions of an immediate operand from two of the instructions [patent_app_type] => utility [patent_app_number] => 15/520168 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 17367 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520168
Method and device for processing an instruction having multi-instruction data including configurably concatenating portions of an immediate operand from two of the instructions Oct 13, 2015 Issued
Array ( [id] => 11945131 [patent_doc_number] => 20170249282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'CONFIGURABLE PRE-PROCESSING ARRAY' [patent_app_type] => utility [patent_app_number] => 15/517266 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7945 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15517266 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/517266
CONFIGURABLE PRE-PROCESSING ARRAY Oct 5, 2015 Abandoned
Array ( [id] => 10771019 [patent_doc_number] => 20160117175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'FREELIST BASED GLOBAL COMPLETION TABLE' [patent_app_type] => utility [patent_app_number] => 14/846892 [patent_app_country] => US [patent_app_date] => 2015-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846892
Freelist based global completion table having both thread-specific and global completion table identifiers Sep 6, 2015 Issued
Array ( [id] => 14034401 [patent_doc_number] => 10228951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-12 [patent_title] => Out of order store commit [patent_app_type] => utility [patent_app_number] => 14/831661 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9286 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831661 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831661
Out of order store commit Aug 19, 2015 Issued
Array ( [id] => 11445132 [patent_doc_number] => 20170046153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/826196 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/826196
SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS Aug 13, 2015 Abandoned
Array ( [id] => 11445137 [patent_doc_number] => 20170046158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'DETERMINING PREFETCH INSTRUCTIONS BASED ON INSTRUCTION ENCODING' [patent_app_type] => utility [patent_app_number] => 14/827245 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6306 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827245 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827245
DETERMINING PREFETCH INSTRUCTIONS BASED ON INSTRUCTION ENCODING Aug 13, 2015 Abandoned
Array ( [id] => 11445147 [patent_doc_number] => 20170046168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'SCALABLE SINGLE-INSTRUCTION-MULTIPLE-DATA INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/827170 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827170
SCALABLE SINGLE-INSTRUCTION-MULTIPLE-DATA INSTRUCTIONS Aug 13, 2015 Abandoned
Array ( [id] => 10808491 [patent_doc_number] => 20160154649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'SWITCHING METHODS FOR CONTEXT MIGRATION AND SYSTEMS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/799899 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6486 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/799899
SWITCHING METHODS FOR CONTEXT MIGRATION AND SYSTEMS THEREOF Jul 14, 2015 Abandoned
Array ( [id] => 10672921 [patent_doc_number] => 20160019066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'EXECUTION OF DIVERGENT THREADS USING A CONVERGENCE BARRIER' [patent_app_type] => utility [patent_app_number] => 14/798265 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798265
Execution of divergent threads using a convergence barrier Jul 12, 2015 Issued
Array ( [id] => 10665726 [patent_doc_number] => 20160011871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Computer Processor Employing Explicit Operations That Support Execution of Software Pipelined Loops and a Compiler That Utilizes Such Operations for Scheduling Software Pipelined Loops' [patent_app_type] => utility [patent_app_number] => 14/797432 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18934 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797432 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/797432
Computer processor employing explicit operations that support execution of software pipelined loops and a compiler that utilizes such operations for scheduling software pipelined loops Jul 12, 2015 Issued
Array ( [id] => 11384917 [patent_doc_number] => 20170010973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'PROCESSOR WITH EFFICIENT PROCESSING OF LOAD-STORE INSTRUCTION PAIRS' [patent_app_type] => utility [patent_app_number] => 14/794853 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14857 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794853 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794853
PROCESSOR WITH EFFICIENT PROCESSING OF LOAD-STORE INSTRUCTION PAIRS Jul 8, 2015 Abandoned
Array ( [id] => 11384838 [patent_doc_number] => 20170010894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'DYNAMIC THREAD SPLITTING' [patent_app_type] => utility [patent_app_number] => 14/794521 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16151 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794521
Dynamic thread splitting having multiple instruction pointers for the same thread Jul 7, 2015 Issued
Array ( [id] => 13679521 [patent_doc_number] => 20160378497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Systems, Methods, and Apparatuses for Thread Selection and Reservation Station Binding [patent_app_type] => utility [patent_app_number] => 14/752745 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752745
Systems, Methods, and Apparatuses for Thread Selection and Reservation Station Binding Jun 25, 2015 Abandoned
Array ( [id] => 13679849 [patent_doc_number] => 20160378661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTION BLOCK ALLOCATION [patent_app_type] => utility [patent_app_number] => 14/752418 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752418 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752418
Instruction block allocation Jun 25, 2015 Issued
Array ( [id] => 13679503 [patent_doc_number] => 20160378488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => ACCESS TO TARGET ADDRESS [patent_app_type] => utility [patent_app_number] => 14/752636 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752636
ACCESS TO TARGET ADDRESS Jun 25, 2015 Abandoned
Array ( [id] => 13679509 [patent_doc_number] => 20160378491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => DETERMINATION OF TARGET LOCATION FOR TRANSFER OF PROCESSOR CONTROL [patent_app_type] => utility [patent_app_number] => 14/752660 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752660
DETERMINATION OF TARGET LOCATION FOR TRANSFER OF PROCESSOR CONTROL Jun 25, 2015 Abandoned
Array ( [id] => 13767293 [patent_doc_number] => 10175988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Explicit instruction scheduler state information for a processor [patent_app_type] => utility [patent_app_number] => 14/752797 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752797
Explicit instruction scheduler state information for a processor Jun 25, 2015 Issued
Array ( [id] => 14825183 [patent_doc_number] => 10409599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Decoding information about a group of instructions including a size of the group of instructions [patent_app_type] => utility [patent_app_number] => 14/752682 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752682 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752682
Decoding information about a group of instructions including a size of the group of instructions Jun 25, 2015 Issued
Array ( [id] => 13679515 [patent_doc_number] => 20160378494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Processing Encoding Format to Interpret Information Regarding a Group of Instructions [patent_app_type] => utility [patent_app_number] => 14/752727 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752727 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752727
Processing an encoding format field to interpret header information regarding a group of instructions Jun 25, 2015 Issued
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