Search

Nathaniel Herzfeld

Examiner (ID: 14578, Phone: (571)272-5899 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
626
Issued Applications
427
Pending Applications
1
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18881298 [patent_doc_number] => 20240004667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => PARALLEL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/369532 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369532
PARALLEL PROCESSING DEVICE Sep 17, 2023 Abandoned
Array ( [id] => 20570494 [patent_doc_number] => 20260064418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => INSTRUCTION CONTROL METHOD, DATA CACHING METHOD, AND RELATED PRODUCTS [patent_app_type] => utility [patent_app_number] => 19/106599 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19106599 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/106599
INSTRUCTION CONTROL METHOD, DATA CACHING METHOD, AND RELATED PRODUCTS Aug 1, 2023 Pending
Array ( [id] => 19756526 [patent_doc_number] => 20250045091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => LOW LATENCY INTER CORE COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/364037 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364037
LOW LATENCY INTER CORE COMMUNICATION Aug 1, 2023 Abandoned
Array ( [id] => 18772771 [patent_doc_number] => 20230367597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 18/227608 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227608
INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR Jul 27, 2023 Pending
Array ( [id] => 19747848 [patent_doc_number] => 20250036413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Measuring Performance Associated with Processing Instructions [patent_app_type] => utility [patent_app_number] => 18/357984 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357984
Measuring Performance Associated with Processing Instructions Jul 23, 2023 Pending
Array ( [id] => 20265775 [patent_doc_number] => 12436766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Sharing branch predictor resource for instruction cache and trace cache predictions [patent_app_type] => utility [patent_app_number] => 18/352351 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 14256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352351
Sharing branch predictor resource for instruction cache and trace cache predictions Jul 13, 2023 Issued
Array ( [id] => 18741695 [patent_doc_number] => 20230350676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Tensor Processing Method, Apparatus, and Device, and Computer-Readable Storage Medium [patent_app_type] => utility [patent_app_number] => 18/350907 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350907
Tensor Processing Method, Apparatus, and Device, and Computer-Readable Storage Medium Jul 11, 2023 Pending
Array ( [id] => 19905764 [patent_doc_number] => 12282772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Vector processor with vector data buffer [patent_app_type] => utility [patent_app_number] => 18/217368 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7581 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217368
Vector processor with vector data buffer Jun 29, 2023 Issued
Array ( [id] => 19099663 [patent_doc_number] => 20240118891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/216780 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216780
Processor selectively executing first instruction using non-pre-processed data or second instruction using pre-processed data Jun 29, 2023 Issued
Array ( [id] => 19686224 [patent_doc_number] => 20250004769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => CRACKING INSTRUCTIONS INTO A PLURALITY OF MICRO-OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/343294 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343294
Cracking instructions into a plurality of micro-operations Jun 27, 2023 Issued
Array ( [id] => 18694930 [patent_doc_number] => 20230325348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PERFORMING CONCURRENT OPERATIONS IN A PROCESSING ELEMENT [patent_app_type] => utility [patent_app_number] => 18/210202 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/210202
PERFORMING CONCURRENT OPERATIONS IN A PROCESSING ELEMENT Jun 14, 2023 Pending
Array ( [id] => 20052031 [patent_doc_number] => 20250190253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => MULTICORE LIFESPAN MANAGEMENT USING EXTRANEOUS CORES [patent_app_type] => utility [patent_app_number] => 18/332819 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332819
MULTICORE LIFESPAN MANAGEMENT USING EXTRANEOUS CORES Jun 11, 2023 Pending
Array ( [id] => 18694771 [patent_doc_number] => 20230325188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND READ/ADVANCE OPERAND CODING [patent_app_type] => utility [patent_app_number] => 18/332817 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332817
Data processing apparatus having streaming engine with read and read/advance operand coding Jun 11, 2023 Issued
Array ( [id] => 19036382 [patent_doc_number] => 20240086197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => COMPUTING DEVICE, COMPUTING METHOD, AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/206163 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206163
Processing call and return information due to a branch prediction error Jun 5, 2023 Issued
Array ( [id] => 20079811 [patent_doc_number] => 12353880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method [patent_app_type] => utility [patent_app_number] => 18/325519 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325519
One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method May 29, 2023 Issued
Array ( [id] => 19617368 [patent_doc_number] => 20240403048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING [patent_app_type] => utility [patent_app_number] => 18/325806 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325806
CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING May 29, 2023 Pending
Array ( [id] => 18864170 [patent_doc_number] => 20230418606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => VECTOR POPULATION COUNT DETERMINATION IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/202161 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202161
Vector population count determination via comparison iterations in memory May 24, 2023 Issued
Array ( [id] => 20110045 [patent_doc_number] => 12360766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Hardware accelerator for execution of instruction set of recurrent neural network, data processing method, system-level chip, and medium thereof [patent_app_type] => utility [patent_app_number] => 18/201755 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 473 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201755
Hardware accelerator for execution of instruction set of recurrent neural network, data processing method, system-level chip, and medium thereof May 23, 2023 Issued
Array ( [id] => 18811286 [patent_doc_number] => 20230385622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NEURAL PROCESSING UNIT INCLUDING INTERNAL MEMORY HAVING SCALABLE BANDWIDTH AND DRIVING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/199291 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199291 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199291
NEURAL PROCESSING UNIT INCLUDING INTERNAL MEMORY HAVING SCALABLE BANDWIDTH AND DRIVING METHOD THEREOF May 17, 2023 Pending
Array ( [id] => 18756045 [patent_doc_number] => 20230359490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => DEVICE, SYSTEM AND METHOD FOR SCHEDULING JOB REQUESTS [patent_app_type] => utility [patent_app_number] => 18/312612 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312612
DEVICE, SYSTEM AND METHOD FOR SCHEDULING JOB REQUESTS May 4, 2023 Abandoned
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