Search

Naum B. Levin

Examiner (ID: 12535, Phone: (571)272-1898 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1562
Issued Applications
1386
Pending Applications
10
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18918463 [patent_doc_number] => 11880743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Synthesis of a quantum circuit [patent_app_type] => utility [patent_app_number] => 18/168138 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16794 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168138
Synthesis of a quantum circuit Feb 12, 2023 Issued
Array ( [id] => 18401252 [patent_doc_number] => 11663390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => Method for placement semiconductor device based on prohibited area information [patent_app_type] => utility [patent_app_number] => 18/154126 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15239 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154126
Method for placement semiconductor device based on prohibited area information Jan 12, 2023 Issued
Array ( [id] => 18796053 [patent_doc_number] => 11829844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Refining qubit calibration models using supervised learning [patent_app_type] => utility [patent_app_number] => 18/088303 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088303
Refining qubit calibration models using supervised learning Dec 22, 2022 Issued
Array ( [id] => 18412677 [patent_doc_number] => 11667208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Distributed on-demand elevated power in low power infrastructures [patent_app_type] => utility [patent_app_number] => 18/086175 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7962 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086175
Distributed on-demand elevated power in low power infrastructures Dec 20, 2022 Issued
Array ( [id] => 18873473 [patent_doc_number] => 11861284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Conductor scheme selection and track planning for mixed-diagonal-manhattan routing [patent_app_type] => utility [patent_app_number] => 17/937654 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 12579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937654
Conductor scheme selection and track planning for mixed-diagonal-manhattan routing Oct 2, 2022 Issued
Array ( [id] => 18678401 [patent_doc_number] => 20230316049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => METHOD FOR AI-BASED CIRCUIT DESIGN AND IMPLEMENTATION SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/950164 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950164
Method for AI-based circuit design and implementation system thereof Sep 21, 2022 Issued
Array ( [id] => 18038734 [patent_doc_number] => 20220382950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/883246 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883246
Method for optimizing floor plan for an integrated circuit Aug 7, 2022 Issued
Array ( [id] => 18635646 [patent_doc_number] => 11760224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Vehicle charging system [patent_app_type] => utility [patent_app_number] => 17/817185 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9785 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/817185
Vehicle charging system Aug 2, 2022 Issued
Array ( [id] => 18038733 [patent_doc_number] => 20220382949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => INTEGRATED CIRCUIT INCLUDING CELLS OF DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/877483 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877483
Integrated circuit including cells of different heights and method of designing the integrated circuit Jul 28, 2022 Issued
Array ( [id] => 18950038 [patent_doc_number] => 11893334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Method for optimizing floor plan for an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/875139 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 11698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875139
Method for optimizing floor plan for an integrated circuit Jul 26, 2022 Issued
Array ( [id] => 18386416 [patent_doc_number] => 11657199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Method for analyzing electromigration (EM) in integrated circuit [patent_app_type] => utility [patent_app_number] => 17/814016 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814016
Method for analyzing electromigration (EM) in integrated circuit Jul 20, 2022 Issued
Array ( [id] => 18668822 [patent_doc_number] => 11775726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Integrated circuit having latch-up immunity [patent_app_type] => utility [patent_app_number] => 17/869229 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869229
Integrated circuit having latch-up immunity Jul 19, 2022 Issued
Array ( [id] => 18607078 [patent_doc_number] => 11748546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => System and method for back side signal routing [patent_app_type] => utility [patent_app_number] => 17/856285 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 13080 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856285
System and method for back side signal routing Jun 30, 2022 Issued
Array ( [id] => 18447322 [patent_doc_number] => 11682901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Airport electric vehicle charging system [patent_app_type] => utility [patent_app_number] => 17/850372 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6922 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850372
Airport electric vehicle charging system Jun 26, 2022 Issued
Array ( [id] => 17887263 [patent_doc_number] => 20220302741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => CHARGING CONTROL FOR IMPROVING EFFICIENCY OF CHARGING AUXILIARY DEVICE BATTERY [patent_app_type] => utility [patent_app_number] => 17/836638 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836638
Charging control for improving efficiency of charging auxiliary device battery Jun 8, 2022 Issued
Array ( [id] => 19078521 [patent_doc_number] => 11947889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Chips placed in full-custom layout and electronic device for implementing mining algorithm [patent_app_type] => utility [patent_app_number] => 18/011699 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 13274 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18011699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/011699
Chips placed in full-custom layout and electronic device for implementing mining algorithm Jan 9, 2022 Issued
Array ( [id] => 18320127 [patent_doc_number] => 20230118255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHOD FOR MODELING SEQUENCE IMPEDANCE OF MODULAR MULTILEVEL CONVERTER UNDER PHASE LOCKED LOOP COUPLING [patent_app_type] => utility [patent_app_number] => 17/771967 [patent_app_country] => US [patent_app_date] => 2021-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/771967
Method for modeling sequence impedance of modular multilevel converter under phase locked loop coupling Dec 10, 2021 Issued
Array ( [id] => 18873472 [patent_doc_number] => 11861283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Placement method and non-transitory computer readable storage medium [patent_app_type] => utility [patent_app_number] => 17/455013 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5584 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455013
Placement method and non-transitory computer readable storage medium Nov 14, 2021 Issued
Array ( [id] => 17446761 [patent_doc_number] => 20220067266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => STANDARD CELLS AND VARIATIONS THEREOF WITHIN A STANDARD CELL LIBRARY [patent_app_type] => utility [patent_app_number] => 17/523600 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523600
Standard cells and variations thereof within a standard cell library Nov 9, 2021 Issued
Array ( [id] => 17794494 [patent_doc_number] => 20220253586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/505683 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505683
Standard cell template and semiconductor structure Oct 19, 2021 Issued
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