Search

Naum B. Levin

Examiner (ID: 12535, Phone: (571)272-1898 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1562
Issued Applications
1386
Pending Applications
10
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18872998 [patent_doc_number] => 11860805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Terminal device, adapter, and charging method [patent_app_type] => utility [patent_app_number] => 17/352908 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5412 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352908
Terminal device, adapter, and charging method Jun 20, 2021 Issued
Array ( [id] => 18734949 [patent_doc_number] => 11803683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Method of and system for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/342295 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342295
Method of and system for manufacturing semiconductor device Jun 7, 2021 Issued
Array ( [id] => 17113610 [patent_doc_number] => 20210294207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => OBTAINING A MASK USING A COST FUNCTION GRADIENT FROM A JACOBIAN MATRIX GENERATED FROM A PERTURBATION LOOK-UP TABLE [patent_app_type] => utility [patent_app_number] => 17/339174 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339174
Obtaining a mask using a cost function gradient from a jacobian matrix generated from a perturbation look-up table Jun 3, 2021 Issued
Array ( [id] => 18174395 [patent_doc_number] => 11574107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Method for manufacturing a cell having pins and semiconductor device based on same [patent_app_type] => utility [patent_app_number] => 17/339162 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 16749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339162 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339162
Method for manufacturing a cell having pins and semiconductor device based on same Jun 3, 2021 Issued
Array ( [id] => 17276854 [patent_doc_number] => 20210383052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => METHOD OF CERTIFYING SAFETY LEVELS OF SEMICONDUCTOR MEMORIES IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/334172 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334172
Method of certifying safety levels of semiconductor memories in integrated circuits May 27, 2021 Issued
Array ( [id] => 18967505 [patent_doc_number] => 11901286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Diagonal via pattern and method [patent_app_type] => utility [patent_app_number] => 17/334320 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 11029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334320
Diagonal via pattern and method May 27, 2021 Issued
Array ( [id] => 17999944 [patent_doc_number] => 11501052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing [patent_app_type] => utility [patent_app_number] => 17/331693 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 12649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331693
Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing May 26, 2021 Issued
Array ( [id] => 17099136 [patent_doc_number] => 20210286927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => PIN ACCESS HYBRID CELL HEIGHT DESIGN [patent_app_type] => utility [patent_app_number] => 17/332646 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332646
Pin access hybrid cell height design May 26, 2021 Issued
Array ( [id] => 18446276 [patent_doc_number] => 11681848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => On-the-fly multi-bit flip flop generation [patent_app_type] => utility [patent_app_number] => 17/318647 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9573 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318647
On-the-fly multi-bit flip flop generation May 11, 2021 Issued
Array ( [id] => 18638450 [patent_doc_number] => 11763055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Reduced-power dynamic data circuits with wide-band energy recovery [patent_app_type] => utility [patent_app_number] => 17/317500 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8315 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317500
Reduced-power dynamic data circuits with wide-band energy recovery May 10, 2021 Issued
Array ( [id] => 18331841 [patent_doc_number] => 11637098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Pin modification for standard cells [patent_app_type] => utility [patent_app_number] => 17/315900 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315900
Pin modification for standard cells May 9, 2021 Issued
Array ( [id] => 18527955 [patent_doc_number] => 11714949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Leakage analysis on semiconductor device [patent_app_type] => utility [patent_app_number] => 17/314988 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314988
Leakage analysis on semiconductor device May 6, 2021 Issued
Array ( [id] => 18387557 [patent_doc_number] => 11658352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => System and method for operating a rechargeable electrochemical cell or battery [patent_app_type] => utility [patent_app_number] => 17/313216 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23781 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313216 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313216
System and method for operating a rechargeable electrochemical cell or battery May 5, 2021 Issued
Array ( [id] => 18370948 [patent_doc_number] => 11651126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Recovery of a hierarchical functional representation of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/239977 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4809 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239977
Recovery of a hierarchical functional representation of an integrated circuit Apr 25, 2021 Issued
Array ( [id] => 17907675 [patent_doc_number] => 11461530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-04 [patent_title] => Circuit design routing based on routing demand adjustment [patent_app_type] => utility [patent_app_number] => 17/231983 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10679 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231983
Circuit design routing based on routing demand adjustment Apr 14, 2021 Issued
Array ( [id] => 17817589 [patent_doc_number] => 11423204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-23 [patent_title] => System and method for back side signal routing [patent_app_type] => utility [patent_app_number] => 17/230393 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 13045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230393
System and method for back side signal routing Apr 13, 2021 Issued
Array ( [id] => 16950586 [patent_doc_number] => 20210209278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD FOR ANALYZING ELECTROMIGRATION (EM) IN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/209393 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209393
Method for analyzing electromigration (EM) in integrated circuit Mar 22, 2021 Issued
Array ( [id] => 17824826 [patent_doc_number] => 11429774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Variable width nano-sheet field-effect transistor cell structure [patent_app_type] => utility [patent_app_number] => 17/199551 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 13458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199551
Variable width nano-sheet field-effect transistor cell structure Mar 11, 2021 Issued
Array ( [id] => 17877644 [patent_doc_number] => 11449660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Method to perform secondary-PG aware buffering in IC design flow [patent_app_type] => utility [patent_app_number] => 17/198132 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 8955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198132
Method to perform secondary-PG aware buffering in IC design flow Mar 9, 2021 Issued
Array ( [id] => 17729861 [patent_doc_number] => 11386252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-12 [patent_title] => Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction [patent_app_type] => utility [patent_app_number] => 17/194358 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 33339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194358
Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction Mar 7, 2021 Issued
Menu