Search

Navneet K. Gmahl

Examiner (ID: 3841, Phone: (571)272-5636 , Office: P/2166 )

Most Active Art Unit
2166
Art Unit(s)
2166
Total Applications
497
Issued Applications
269
Pending Applications
40
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4857928 [patent_doc_number] => 20080266778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Memory module routing' [patent_app_type] => utility [patent_app_number] => 12/052804 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5539 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266778.pdf [firstpage_image] =>[orig_patent_app_number] => 12052804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/052804
Memory module routing Mar 20, 2008 Abandoned
Array ( [id] => 192027 [patent_doc_number] => 07643346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells' [patent_app_type] => utility [patent_app_number] => 12/052149 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 11457 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/643/07643346.pdf [firstpage_image] =>[orig_patent_app_number] => 12052149 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/052149
NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells Mar 19, 2008 Issued
Array ( [id] => 4811901 [patent_doc_number] => 20080192532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'HYBRID CIRCUIT HAVING NANOTUBE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 12/030470 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6464 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20080192532.pdf [firstpage_image] =>[orig_patent_app_number] => 12030470 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030470
Hybrid circuit having nanotube memory cells Feb 12, 2008 Issued
Array ( [id] => 4598569 [patent_doc_number] => 07983068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Memory element with positive temperature coefficient layer' [patent_app_type] => utility [patent_app_number] => 12/030059 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 5564 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983068.pdf [firstpage_image] =>[orig_patent_app_number] => 12030059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030059
Memory element with positive temperature coefficient layer Feb 11, 2008 Issued
Array ( [id] => 4723833 [patent_doc_number] => 20080203374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Phase-change memory and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/010885 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203374.pdf [firstpage_image] =>[orig_patent_app_number] => 12010885 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010885
Phase-change memory and fabrication method thereof Jan 29, 2008 Abandoned
Array ( [id] => 4844639 [patent_doc_number] => 20080181047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/010674 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4737 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20080181047.pdf [firstpage_image] =>[orig_patent_app_number] => 12010674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010674
Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system Jan 28, 2008 Issued
Array ( [id] => 36146 [patent_doc_number] => 07787326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Programmable logic device with a multi-data rate SDRAM interface' [patent_app_type] => utility [patent_app_number] => 12/019526 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4278 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787326.pdf [firstpage_image] =>[orig_patent_app_number] => 12019526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019526
Programmable logic device with a multi-data rate SDRAM interface Jan 23, 2008 Issued
Array ( [id] => 4435910 [patent_doc_number] => 07969785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-28 [patent_title] => 'Low voltage non-volatile memory with charge trapping layer' [patent_app_type] => utility [patent_app_number] => 12/009723 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5026 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969785.pdf [firstpage_image] =>[orig_patent_app_number] => 12009723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/009723
Low voltage non-volatile memory with charge trapping layer Jan 21, 2008 Issued
Array ( [id] => 4458983 [patent_doc_number] => 07894257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-22 [patent_title] => 'Low voltage low cost non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/009663 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4829 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894257.pdf [firstpage_image] =>[orig_patent_app_number] => 12009663 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/009663
Low voltage low cost non-volatile memory Jan 21, 2008 Issued
Array ( [id] => 4458961 [patent_doc_number] => 07894246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Magnetoresistive element and magnetic memory' [patent_app_type] => utility [patent_app_number] => 12/014522 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 9552 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894246.pdf [firstpage_image] =>[orig_patent_app_number] => 12014522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014522
Magnetoresistive element and magnetic memory Jan 14, 2008 Issued
Array ( [id] => 6575475 [patent_doc_number] => 20100096715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 12/529387 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7323 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20100096715.pdf [firstpage_image] =>[orig_patent_app_number] => 12529387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/529387
MRAM utilizing free layer having fixed magnetization regions with larger damping coefficient than the switching region Jan 14, 2008 Issued
Array ( [id] => 5351370 [patent_doc_number] => 20090006731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/967587 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3217 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006731.pdf [firstpage_image] =>[orig_patent_app_number] => 11967587 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967587
Semiconductor memory device having common circuitry for controlling address and data mask information Dec 30, 2007 Issued
Array ( [id] => 7541610 [patent_doc_number] => 08059458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => '3T high density nvDRAM cell' [patent_app_type] => utility [patent_app_number] => 12/006227 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4593 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/059/08059458.pdf [firstpage_image] =>[orig_patent_app_number] => 12006227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006227
3T high density nvDRAM cell Dec 30, 2007 Issued
Array ( [id] => 289825 [patent_doc_number] => 07548444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Memory module and memory device' [patent_app_type] => utility [patent_app_number] => 12/003707 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 15521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/548/07548444.pdf [firstpage_image] =>[orig_patent_app_number] => 12003707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003707
Memory module and memory device Dec 30, 2007 Issued
Array ( [id] => 5584183 [patent_doc_number] => 20090103385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES' [patent_app_type] => utility [patent_app_number] => 11/965753 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1712 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103385.pdf [firstpage_image] =>[orig_patent_app_number] => 11965753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965753
Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules Dec 27, 2007 Issued
Array ( [id] => 44962 [patent_doc_number] => 07782649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Using controlled bias voltage for data retention enhancement in a ferroelectric media' [patent_app_type] => utility [patent_app_number] => 11/961973 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782649.pdf [firstpage_image] =>[orig_patent_app_number] => 11961973 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961973
Using controlled bias voltage for data retention enhancement in a ferroelectric media Dec 19, 2007 Issued
Array ( [id] => 4913517 [patent_doc_number] => 20080094116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'CLOCK GENERATING CIRCUIT WITH MULTIPLE MODES OF OPERATION' [patent_app_type] => utility [patent_app_number] => 11/957333 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6358 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094116.pdf [firstpage_image] =>[orig_patent_app_number] => 11957333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957333
Clock generating circuit with multiple modes of operation Dec 13, 2007 Issued
Array ( [id] => 5430164 [patent_doc_number] => 20090089474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORY' [patent_app_type] => utility [patent_app_number] => 11/954235 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 950 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089474.pdf [firstpage_image] =>[orig_patent_app_number] => 11954235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954235
MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORY Dec 11, 2007 Abandoned
Array ( [id] => 5427251 [patent_doc_number] => 20090086561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES' [patent_app_type] => utility [patent_app_number] => 11/952140 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1636 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20090086561.pdf [firstpage_image] =>[orig_patent_app_number] => 11952140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952140
Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules Dec 6, 2007 Issued
Array ( [id] => 4784060 [patent_doc_number] => 20080137389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Multi-stack memory device' [patent_app_type] => utility [patent_app_number] => 11/978583 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6978 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137389.pdf [firstpage_image] =>[orig_patent_app_number] => 11978583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978583
Multi-stack memory device Oct 29, 2007 Issued
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