Search

Navneet K. Gmahl

Examiner (ID: 3841, Phone: (571)272-5636 , Office: P/2166 )

Most Active Art Unit
2166
Art Unit(s)
2166
Total Applications
497
Issued Applications
269
Pending Applications
40
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4890728 [patent_doc_number] => 20080099825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Nonvolatile semiconductor memory device and method of producing the same' [patent_app_type] => utility [patent_app_number] => 11/976496 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7363 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099825.pdf [firstpage_image] =>[orig_patent_app_number] => 11976496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976496
Nonvolatile semiconductor memory device and method of producing the same Oct 24, 2007 Abandoned
Array ( [id] => 338951 [patent_doc_number] => 07505296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Ternary content addressable memory with block encoding' [patent_app_type] => utility [patent_app_number] => 11/877310 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 18000 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505296.pdf [firstpage_image] =>[orig_patent_app_number] => 11877310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877310
Ternary content addressable memory with block encoding Oct 22, 2007 Issued
Array ( [id] => 4438717 [patent_doc_number] => 07898850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells' [patent_app_type] => utility [patent_app_number] => 11/871339 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9318 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898850.pdf [firstpage_image] =>[orig_patent_app_number] => 11871339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/871339
Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells Oct 11, 2007 Issued
Array ( [id] => 73991 [patent_doc_number] => 07755926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => '3-D SRAM array to improve stability and performance' [patent_app_type] => utility [patent_app_number] => 11/867877 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7486 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755926.pdf [firstpage_image] =>[orig_patent_app_number] => 11867877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867877
3-D SRAM array to improve stability and performance Oct 4, 2007 Issued
Array ( [id] => 66430 [patent_doc_number] => 07760533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Systems, methods and devices for arbitrating die stack position in a multi-bit stack device' [patent_app_type] => utility [patent_app_number] => 11/906673 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4379 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/760/07760533.pdf [firstpage_image] =>[orig_patent_app_number] => 11906673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906673
Systems, methods and devices for arbitrating die stack position in a multi-bit stack device Oct 1, 2007 Issued
Array ( [id] => 5426294 [patent_doc_number] => 20090085604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MULTIPLE ADDRESS OUTPUTS FOR PROGRAMMING THE MEMORY REGISTER SET DIFFERENTLY FOR DIFFERENT DRAM DEVICES' [patent_app_type] => utility [patent_app_number] => 11/863106 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085604.pdf [firstpage_image] =>[orig_patent_app_number] => 11863106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863106
Multiple address outputs for programming the memory register set differently for different DRAM devices Sep 26, 2007 Issued
Array ( [id] => 34941 [patent_doc_number] => 07791918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Stack position location identification for memory stacked packages' [patent_app_type] => utility [patent_app_number] => 11/862802 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1820 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791918.pdf [firstpage_image] =>[orig_patent_app_number] => 11862802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862802
Stack position location identification for memory stacked packages Sep 26, 2007 Issued
Array ( [id] => 4920586 [patent_doc_number] => 20080068900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'MEMORY MODULE DECODER' [patent_app_type] => utility [patent_app_number] => 11/862931 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16014 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068900.pdf [firstpage_image] =>[orig_patent_app_number] => 11862931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862931
Memory module decoder Sep 26, 2007 Issued
Array ( [id] => 4452942 [patent_doc_number] => 07965567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Phase adjustment apparatus and method for a memory device signaling system' [patent_app_type] => utility [patent_app_number] => 11/855993 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 52 [patent_no_of_words] => 42836 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965567.pdf [firstpage_image] =>[orig_patent_app_number] => 11855993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855993
Phase adjustment apparatus and method for a memory device signaling system Sep 13, 2007 Issued
Array ( [id] => 4702297 [patent_doc_number] => 20080061819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'MEMORY CHIP HAVING A COMPLEX TERMINATION' [patent_app_type] => utility [patent_app_number] => 11/851952 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3925 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061819.pdf [firstpage_image] =>[orig_patent_app_number] => 11851952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851952
Memory chip having a complex termination Sep 6, 2007 Issued
Array ( [id] => 5450511 [patent_doc_number] => 20090066547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/851649 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20090066547.pdf [firstpage_image] =>[orig_patent_app_number] => 11851649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851649
Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device Sep 6, 2007 Issued
Array ( [id] => 4544638 [patent_doc_number] => 07889593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Method and apparatus for generating a sequence of clock signals' [patent_app_type] => utility [patent_app_number] => 11/897837 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5825 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889593.pdf [firstpage_image] =>[orig_patent_app_number] => 11897837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/897837
Method and apparatus for generating a sequence of clock signals Aug 30, 2007 Issued
Array ( [id] => 4744518 [patent_doc_number] => 20080089120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Resistive memory devices having a CMOS compatible electrolyte layer and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/896215 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3519 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089120.pdf [firstpage_image] =>[orig_patent_app_number] => 11896215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896215
Resistive memory devices having a CMOS compatible electrolyte layer and methods of operating the same Aug 29, 2007 Abandoned
Array ( [id] => 4587709 [patent_doc_number] => 07835210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Magnetic random access memory and data read method of the same' [patent_app_type] => utility [patent_app_number] => 11/846985 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/835/07835210.pdf [firstpage_image] =>[orig_patent_app_number] => 11846985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846985
Magnetic random access memory and data read method of the same Aug 28, 2007 Issued
Array ( [id] => 4435916 [patent_doc_number] => 07969788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Charge loss compensation methods and apparatus' [patent_app_type] => utility [patent_app_number] => 11/894377 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3818 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969788.pdf [firstpage_image] =>[orig_patent_app_number] => 11894377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/894377
Charge loss compensation methods and apparatus Aug 20, 2007 Issued
Array ( [id] => 7551912 [patent_doc_number] => 08064249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Nanowire electromechanical switching device, method of manufacturing the same and electromechanical memory device using the nanowire electromechanical switching device' [patent_app_type] => utility [patent_app_number] => 11/889515 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 6900 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064249.pdf [firstpage_image] =>[orig_patent_app_number] => 11889515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889515
Nanowire electromechanical switching device, method of manufacturing the same and electromechanical memory device using the nanowire electromechanical switching device Aug 13, 2007 Issued
Array ( [id] => 4584585 [patent_doc_number] => 07826272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/889159 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5003 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826272.pdf [firstpage_image] =>[orig_patent_app_number] => 11889159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889159
Semiconductor memory device Aug 8, 2007 Issued
Array ( [id] => 44967 [patent_doc_number] => 07782650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same' [patent_app_type] => utility [patent_app_number] => 11/835845 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 217 [patent_figures_cnt] => 259 [patent_no_of_words] => 93392 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782650.pdf [firstpage_image] =>[orig_patent_app_number] => 11835845 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/835845
Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same Aug 7, 2007 Issued
Array ( [id] => 5418094 [patent_doc_number] => 20090043981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'MEMORY CONTROL CIRCUIT CAPABLE OF DYNAMICALLY ADJUSTING DEGLITCH WINDOWS, AND RELATED METHOD' [patent_app_type] => utility [patent_app_number] => 11/835423 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20090043981.pdf [firstpage_image] =>[orig_patent_app_number] => 11835423 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/835423
Memory control circuit capable of dynamically adjusting deglitch windows, and related method Aug 7, 2007 Issued
Array ( [id] => 4587472 [patent_doc_number] => 07835170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks' [patent_app_type] => utility [patent_app_number] => 11/835613 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 52 [patent_no_of_words] => 26925 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/835/07835170.pdf [firstpage_image] =>[orig_patent_app_number] => 11835613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/835613
Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks Aug 7, 2007 Issued
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