Search

Navneet K. Gmahl

Examiner (ID: 3841, Phone: (571)272-5636 , Office: P/2166 )

Most Active Art Unit
2166
Art Unit(s)
2166
Total Applications
497
Issued Applications
269
Pending Applications
40
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4870685 [patent_doc_number] => 20080197419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Cell structure for dual port SRAM' [patent_app_type] => utility [patent_app_number] => 11/787677 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3034 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197419.pdf [firstpage_image] =>[orig_patent_app_number] => 11787677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787677
Cell structure of dual port SRAM Apr 16, 2007 Issued
Array ( [id] => 5044768 [patent_doc_number] => 20070263440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Multi-Chip Package for a Flash Memory' [patent_app_type] => utility [patent_app_number] => 11/694779 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17530 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263440.pdf [firstpage_image] =>[orig_patent_app_number] => 11694779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694779
Multi-chip package for a flash memory Mar 29, 2007 Issued
Array ( [id] => 279021 [patent_doc_number] => 07558103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Magnetic switching element and signal processing device using the same' [patent_app_type] => utility [patent_app_number] => 11/729982 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 63 [patent_no_of_words] => 19191 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558103.pdf [firstpage_image] =>[orig_patent_app_number] => 11729982 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729982
Magnetic switching element and signal processing device using the same Mar 29, 2007 Issued
Array ( [id] => 4801790 [patent_doc_number] => 20080013377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Non-volatile memory devices including dummy word lines and related structures and methods' [patent_app_type] => utility [patent_app_number] => 11/729169 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16335 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20080013377.pdf [firstpage_image] =>[orig_patent_app_number] => 11729169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729169
Non-volatile memory devices including dummy word lines and related structures and methods Mar 27, 2007 Issued
Array ( [id] => 4565318 [patent_doc_number] => 07821864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Power management of memory via wake/sleep cycles' [patent_app_type] => utility [patent_app_number] => 11/691321 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4834 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821864.pdf [firstpage_image] =>[orig_patent_app_number] => 11691321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691321
Power management of memory via wake/sleep cycles Mar 25, 2007 Issued
Array ( [id] => 5407320 [patent_doc_number] => 20090121218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'METHOD FOR PROGRAMMING AN ELECTRONIC CIRCUIT AND ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/293852 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6041 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121218.pdf [firstpage_image] =>[orig_patent_app_number] => 12293852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/293852
Method for programming an electronic circuit and electronic circuit Mar 20, 2007 Issued
Array ( [id] => 36074 [patent_doc_number] => 07787287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Magnetic storage device with curved interconnects' [patent_app_type] => utility [patent_app_number] => 11/723209 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 53 [patent_no_of_words] => 11854 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787287.pdf [firstpage_image] =>[orig_patent_app_number] => 11723209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723209
Magnetic storage device with curved interconnects Mar 18, 2007 Issued
Array ( [id] => 4977425 [patent_doc_number] => 20070218658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Crystallization pattern and method for crystallizing amorphous silicon using the same' [patent_app_type] => utility [patent_app_number] => 11/725123 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4067 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218658.pdf [firstpage_image] =>[orig_patent_app_number] => 11725123 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725123
Crystallization pattern and method for crystallizing amorphous silicon using the same Mar 15, 2007 Issued
Array ( [id] => 4817475 [patent_doc_number] => 20080224734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Multi-terminal chalcogenide logic circuits' [patent_app_type] => utility [patent_app_number] => 11/724485 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16424 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224734.pdf [firstpage_image] =>[orig_patent_app_number] => 11724485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724485
Multi-terminal chalcogenide logic circuits Mar 14, 2007 Issued
Array ( [id] => 5129061 [patent_doc_number] => 20070205458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Non-Volatile Semiconductor Memory and Manufacturing Process Thereof' [patent_app_type] => utility [patent_app_number] => 11/681209 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3786 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205458.pdf [firstpage_image] =>[orig_patent_app_number] => 11681209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/681209
Non-Volatile Semiconductor Memory and Manufacturing Process Thereof Mar 1, 2007 Abandoned
Array ( [id] => 4987228 [patent_doc_number] => 20070153566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Static random access memory cell' [patent_app_type] => utility [patent_app_number] => 11/712751 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153566.pdf [firstpage_image] =>[orig_patent_app_number] => 11712751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712751
Static random access memory cell Feb 27, 2007 Issued
Array ( [id] => 204582 [patent_doc_number] => 07633793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Static random access memory cell' [patent_app_type] => utility [patent_app_number] => 11/712764 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6527 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633793.pdf [firstpage_image] =>[orig_patent_app_number] => 11712764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712764
Static random access memory cell Feb 27, 2007 Issued
Array ( [id] => 5021142 [patent_doc_number] => 20070147108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Static random access memory cell' [patent_app_type] => utility [patent_app_number] => 11/713059 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147108.pdf [firstpage_image] =>[orig_patent_app_number] => 11713059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/713059
Static random access memory cell Feb 27, 2007 Issued
Array ( [id] => 6538913 [patent_doc_number] => 20100271057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit' [patent_app_type] => utility [patent_app_number] => 11/679406 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271057.pdf [firstpage_image] =>[orig_patent_app_number] => 11679406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679406
Method for QCRIT measurement in bulk CMOS using a switched capacitor circuit Feb 26, 2007 Issued
Array ( [id] => 46506 [patent_doc_number] => 07778057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'PCB circuit modification from multiple to individual chip enable signals' [patent_app_type] => utility [patent_app_number] => 11/679157 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 7200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778057.pdf [firstpage_image] =>[orig_patent_app_number] => 11679157 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679157
PCB circuit modification from multiple to individual chip enable signals Feb 25, 2007 Issued
Array ( [id] => 35042 [patent_doc_number] => 07791959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Memory integrated circuit device providing improved operation speed at lower temperature' [patent_app_type] => utility [patent_app_number] => 11/708321 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10121 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791959.pdf [firstpage_image] =>[orig_patent_app_number] => 11708321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708321
Memory integrated circuit device providing improved operation speed at lower temperature Feb 20, 2007 Issued
Array ( [id] => 5118318 [patent_doc_number] => 20070140032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Sensing Current Recycling Method During Self-Refresh' [patent_app_type] => utility [patent_app_number] => 11/677457 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4549 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20070140032.pdf [firstpage_image] =>[orig_patent_app_number] => 11677457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677457
Sensing Current Recycling Method During Self-Refresh Feb 20, 2007 Abandoned
Array ( [id] => 5251838 [patent_doc_number] => 20070133294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'FLASH MEMORY PROGRAMMING TO REDUCE PROGRAM DISTURB' [patent_app_type] => utility [patent_app_number] => 11/675151 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2867 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133294.pdf [firstpage_image] =>[orig_patent_app_number] => 11675151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675151
Flash memory programming to reduce program disturb Feb 14, 2007 Issued
Array ( [id] => 4961628 [patent_doc_number] => 20080276053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Portable Device and Method for Controlling Deep Power Down Mode of Shared Memory' [patent_app_type] => utility [patent_app_number] => 12/094060 [patent_app_country] => US [patent_app_date] => 2007-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276053.pdf [firstpage_image] =>[orig_patent_app_number] => 12094060 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/094060
Portable Device and Method for Controlling Deep Power Down Mode of Shared Memory Feb 2, 2007 Abandoned
Array ( [id] => 4942921 [patent_doc_number] => 20080080246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Flash memory device which includes strapping line connected to selection line' [patent_app_type] => utility [patent_app_number] => 11/657077 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4055 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080246.pdf [firstpage_image] =>[orig_patent_app_number] => 11657077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657077
Flash memory device which includes strapping line connected to selection line Jan 23, 2007 Issued
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