Navneet K. Gmahl

Array ( [id] => 212479 [patent_doc_number] => 07623391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-24 [patent_title] => 'Data transfer verification systems and methods' [patent_app_type] => utility [patent_app_number] => 11/624021 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/623/07623391.pdf [firstpage_image] =>[orig_patent_app_number] => 11624021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 153791 [patent_doc_number] => 07684228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Device and method for using dynamic cell plate sensing in a DRAM memory cell' [patent_app_type] => utility [patent_app_number] => 11/653590 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7072 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/684/07684228.pdf [firstpage_image] =>[orig_patent_app_number] => 11653590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5078185 [patent_doc_number] => 20070121409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method and System for Providing Independent Bank Refresh for Volatile Memories' [patent_app_type] => utility [patent_app_number] => 11/623366 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121409.pdf [firstpage_image] =>[orig_patent_app_number] => 11623366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 55523 [patent_doc_number] => 07773403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Spacer patterns using assist layer for high density semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/623315 [patent_app_country] => US [patent_app_date] => 2007-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6826 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773403.pdf [firstpage_image] =>[orig_patent_app_number] => 11623315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4969868 [patent_doc_number] => 20070109870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/652023 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15203 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109870.pdf [firstpage_image] =>[orig_patent_app_number] => 11652023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5214937 [patent_doc_number] => 20070104017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Memory controller and memory system' [patent_app_type] => utility [patent_app_number] => 11/644222 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104017.pdf [firstpage_image] =>[orig_patent_app_number] => 11644222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5033223 [patent_doc_number] => 20070097762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor storage device, redundancy circuit thereof, and portable electronic device' [patent_app_type] => utility [patent_app_number] => 11/641739 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20672 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097762.pdf [firstpage_image] =>[orig_patent_app_number] => 11641739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 179033 [patent_doc_number] => 07656744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Memory module with load capacitance added to clock signal input' [patent_app_type] => utility [patent_app_number] => 11/611036 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6553 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656744.pdf [firstpage_image] =>[orig_patent_app_number] => 11611036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4981678 [patent_doc_number] => 20070086236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'MRAM memory cell having a weak intrinsic anisotropic storage layer and method of producing the same' [patent_app_type] => utility [patent_app_number] => 11/634988 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5009 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20070086236.pdf [firstpage_image] =>[orig_patent_app_number] => 11634988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 327679 [patent_doc_number] => 07515460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Multilevel programming of phase change memory cells' [patent_app_type] => utility [patent_app_number] => 11/606762 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3212 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515460.pdf [firstpage_image] =>[orig_patent_app_number] => 11606762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4822991 [patent_doc_number] => 20080123305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Multi-channel memory modules for computing devices' [patent_app_type] => utility [patent_app_number] => 11/605809 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20080123305.pdf [firstpage_image] =>[orig_patent_app_number] => 11605809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5134859 [patent_doc_number] => 20070076488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'NON-VOLATILE MEMORY DEVICE CAPABLE OF CHANGING INCREMENT OF PROGRAM VOLTAGE ACCORDING TO MODE OF OPERATION' [patent_app_type] => utility [patent_app_number] => 11/561807 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4663 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076488.pdf [firstpage_image] =>[orig_patent_app_number] => 11561807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 135457 [patent_doc_number] => 07697352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Read-and-write assembly for fixed-address digital data access system' [patent_app_type] => utility [patent_app_number] => 11/558862 [patent_app_country] => US [patent_app_date] => 2006-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4715 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/697/07697352.pdf [firstpage_image] =>[orig_patent_app_number] => 11558862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5184438 [patent_doc_number] => 20070055792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Memory device having terminals for transferring multiple types of data' [patent_app_type] => utility [patent_app_number] => 11/590364 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9449 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20070055792.pdf [firstpage_image] =>[orig_patent_app_number] => 11590364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 578575 [patent_doc_number] => 07466606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Memory device having terminals for transferring multiple types of data' [patent_app_type] => utility [patent_app_number] => 11/590051 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9447 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466606.pdf [firstpage_image] =>[orig_patent_app_number] => 11590051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5099967 [patent_doc_number] => 20070183228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'CONTROL SIGNAL INTERFACE CIRCUIT FOR COMPUTER MEMORY MODULES' [patent_app_type] => utility [patent_app_number] => 11/553441 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4452 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183228.pdf [firstpage_image] =>[orig_patent_app_number] => 11553441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 413350 [patent_doc_number] => 07283411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Flood mode implementation for continuous bitline local evaluation circuit' [patent_app_type] => utility [patent_app_number] => 11/552791 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283411.pdf [firstpage_image] =>[orig_patent_app_number] => 11552791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4892050 [patent_doc_number] => 20080101147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Clock and Power Fault Detection for Memory Modules' [patent_app_type] => utility [patent_app_number] => 11/552949 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101147.pdf [firstpage_image] =>[orig_patent_app_number] => 11552949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1077955 [patent_doc_number] => 07616472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method and apparatus for non-volatile multi-bit memory' [patent_app_type] => utility [patent_app_number] => 11/552032 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/616/07616472.pdf [firstpage_image] =>[orig_patent_app_number] => 11552032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 135471 [patent_doc_number] => 07697362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Arbitration for memory device with commands' [patent_app_type] => utility [patent_app_number] => 11/521655 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6473 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/697/07697362.pdf [firstpage_image] =>[orig_patent_app_number] => 11521655 [rel_patent_id] =>[rel_patent_doc_number] =>)