Nduka E. Ojeh

Array ( [id] => 10343703 [patent_doc_number] => 20150228708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'TUNABLE POLY RESISTORS FOR HYBRID REPLACEMENT GATE TECHNOLOGY AND METHODS OF MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 14/176746 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10343567 [patent_doc_number] => 20150228572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'NANOSCALE INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/176228 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10016230 [patent_doc_number] => 09059252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Silicon waveguide on bulk silicon substrate and methods of forming' [patent_app_type] => utility [patent_app_number] => 14/176552 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4420 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10343550 [patent_doc_number] => 20150228555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'STRUCTURE AND METHOD OF CANCELLING TSV-INDUCED SUBSTRATE STRESS' [patent_app_type] => utility [patent_app_number] => 14/176178 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10336587 [patent_doc_number] => 20150221592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES' [patent_app_type] => utility [patent_app_number] => 14/170651 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10336494 [patent_doc_number] => 20150221499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'METHOD FOR PASSIVATING SURFACES, FUNCTIONALIZING INERT SURFACES, LAYERS AND DEVICES INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 14/170058 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11391929 [patent_doc_number] => 09553179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Semiconductor device and insulated gate bipolar transistor with barrier structure' [patent_app_type] => utility [patent_app_number] => 14/169712 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 8424 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10336810 [patent_doc_number] => 20150221815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SOLID STATE LIGHTING DEVICE WITH REDUCED LUMINOUS FLUX DROP AT ELEVATED TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 14/170176 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14432 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10336571 [patent_doc_number] => 20150221576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'Heat Dissipation Structure for Semiconductor Element' [patent_app_type] => utility [patent_app_number] => 14/169408 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1550 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329357 [patent_doc_number] => 20150214361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'Semiconductor Device Having Partial Insulation Structure And Method Of Fabricating Same' [patent_app_type] => utility [patent_app_number] => 14/168969 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12457665 [patent_doc_number] => 09985094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Super junction with an angled trench, transistor having the super junction and method of making the same [patent_app_type] => utility [patent_app_number] => 14/141720 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10303046 [patent_doc_number] => 20150188046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHODS, SYSTEMS, AND APPARATUS FOR IMPROVING THIN FILM RESISTOR RELIABILITY' [patent_app_type] => utility [patent_app_number] => 14/141627 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8477 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10531393 [patent_doc_number] => 09257537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Finfet including improved epitaxial topology' [patent_app_type] => utility [patent_app_number] => 14/141575 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2652 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11701838 [patent_doc_number] => 09691763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Multi-gate FinFET semiconductor device with flexible design width' [patent_app_type] => utility [patent_app_number] => 14/141593 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4160 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302681 [patent_doc_number] => 20150187681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'FLEXIBLE MICROELECTRONIC ASSEMBLY AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/141123 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4932 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11638078 [patent_doc_number] => 09660064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack' [patent_app_type] => utility [patent_app_number] => 14/141304 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 12720 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302578 [patent_doc_number] => 20150187578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD OF FORMING SILICON LAYER, AND METHOD OF MANUFACTURING FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 14/141244 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2218 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302608 [patent_doc_number] => 20150187608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'DIE PACKAGE ARCHITECTURE WITH EMBEDDED DIE AND SIMPLIFIED REDISTRIBUTION LAYER' [patent_app_type] => utility [patent_app_number] => 14/141343 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8976 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433469 [patent_doc_number] => 20150318481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'AN ORGANIC POLYMER PHOTO DEVICE WITH BROADBAND RESPONSE AND INCREASED PHOTO-RESPONSITIVITY' [patent_app_type] => utility [patent_app_number] => 14/649049 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4276 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14649049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10165381 [patent_doc_number] => 09196613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Stress inducing contact metal in FinFET CMOS' [patent_app_type] => utility [patent_app_number] => 14/083544 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7082 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083544 [rel_patent_id] =>[rel_patent_doc_number] =>)