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Ned Andrew Walker

Examiner (ID: 14953)

Most Active Art Unit
3788
Art Unit(s)
3781, 3788
Total Applications
493
Issued Applications
203
Pending Applications
5
Abandoned Applications
285

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4558697 [patent_doc_number] => 07821142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Intermediate semiconductor device structures' [patent_app_type] => utility [patent_app_number] => 12/145022 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5528 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821142.pdf [firstpage_image] =>[orig_patent_app_number] => 12145022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145022
Intermediate semiconductor device structures Jun 23, 2008 Issued
Array ( [id] => 4708132 [patent_doc_number] => 20080296658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'PROCESS FOR MANUFACTURING A MEMORY DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND COMPRISING NANOCRISTAL MEMORY CELLS AND CMOS TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/129014 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3922 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296658.pdf [firstpage_image] =>[orig_patent_app_number] => 12129014 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129014
Process for manufacturing a memory device integrated on a semiconductor substrate and comprising nanocrystal memory cells and CMOS transistors May 28, 2008 Issued
Array ( [id] => 5488235 [patent_doc_number] => 20090289306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'LATERAL OXIDATION WITH HIGH-K DIELECTRIC LINER' [patent_app_type] => utility [patent_app_number] => 12/124794 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289306.pdf [firstpage_image] =>[orig_patent_app_number] => 12124794 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124794
Lateral oxidation with high-K dielectric liner May 20, 2008 Issued
Array ( [id] => 7490551 [patent_doc_number] => 08030207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Method of manufacturing a semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/110662 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 4472 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030207.pdf [firstpage_image] =>[orig_patent_app_number] => 12110662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110662
Method of manufacturing a semiconductor device and semiconductor device Apr 27, 2008 Issued
Array ( [id] => 5555572 [patent_doc_number] => 20090267149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS' [patent_app_type] => utility [patent_app_number] => 12/109025 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6138 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267149.pdf [firstpage_image] =>[orig_patent_app_number] => 12109025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109025
Source/drain junction for high performance MOSFET formed by selective EPI process Apr 23, 2008 Issued
Array ( [id] => 7492386 [patent_doc_number] => 08030751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Board-on-chip type substrates with conductive traces in multiple planes and semiconductor device packages including such substrates' [patent_app_type] => utility [patent_app_number] => 12/106845 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3452 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030751.pdf [firstpage_image] =>[orig_patent_app_number] => 12106845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106845
Board-on-chip type substrates with conductive traces in multiple planes and semiconductor device packages including such substrates Apr 20, 2008 Issued
Array ( [id] => 4822173 [patent_doc_number] => 20080227290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Semiconductor Device and Method for Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 11/967334 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2149 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20080227290.pdf [firstpage_image] =>[orig_patent_app_number] => 11967334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967334
Semiconductor device including contact pattern and method for fabricating the same Dec 30, 2007 Issued
Array ( [id] => 4762807 [patent_doc_number] => 20080174016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Flexible Printed Wiring Board and Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/965404 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 19772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20080174016.pdf [firstpage_image] =>[orig_patent_app_number] => 11965404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965404
Flexible Printed Wiring Board and Semiconductor Device Dec 26, 2007 Abandoned
Array ( [id] => 220945 [patent_doc_number] => 07608491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas' [patent_app_type] => utility [patent_app_number] => 11/959924 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2440 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608491.pdf [firstpage_image] =>[orig_patent_app_number] => 11959924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959924
Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas Dec 18, 2007 Issued
Array ( [id] => 5546106 [patent_doc_number] => 20090155983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'INHIBITION OF METAL DIFFUSION ARISING FROM LASER DICING' [patent_app_type] => utility [patent_app_number] => 11/955484 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2384 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20090155983.pdf [firstpage_image] =>[orig_patent_app_number] => 11955484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955484
Method of inhibition of metal diffusion arising from laser dicing Dec 12, 2007 Issued
Array ( [id] => 292325 [patent_doc_number] => 07544615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Systems and methods of forming refractory metal nitride layers using organic amines' [patent_app_type] => utility [patent_app_number] => 11/943688 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7623 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/544/07544615.pdf [firstpage_image] =>[orig_patent_app_number] => 11943688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943688
Systems and methods of forming refractory metal nitride layers using organic amines Nov 20, 2007 Issued
Array ( [id] => 1076972 [patent_doc_number] => 07615485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method of manufacture of contact plug and interconnection layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/877833 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 61 [patent_no_of_words] => 5578 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615485.pdf [firstpage_image] =>[orig_patent_app_number] => 11877833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877833
Method of manufacture of contact plug and interconnection layer of semiconductor device Oct 23, 2007 Issued
Array ( [id] => 4472449 [patent_doc_number] => 07944033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Power semiconductor module' [patent_app_type] => utility [patent_app_number] => 11/874538 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5933 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944033.pdf [firstpage_image] =>[orig_patent_app_number] => 11874538 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874538
Power semiconductor module Oct 17, 2007 Issued
Array ( [id] => 243284 [patent_doc_number] => 07589018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method of forming contact hole, method of manufacturing wiring board, method of manufacturing semiconductor device, and method of manufacturing electro-optical device' [patent_app_type] => utility [patent_app_number] => 11/973193 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 97 [patent_no_of_words] => 18947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589018.pdf [firstpage_image] =>[orig_patent_app_number] => 11973193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973193
Method of forming contact hole, method of manufacturing wiring board, method of manufacturing semiconductor device, and method of manufacturing electro-optical device Oct 4, 2007 Issued
Array ( [id] => 4648795 [patent_doc_number] => 20080036050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Package with solder-filled via holes in molding layers' [patent_app_type] => utility [patent_app_number] => 11/880753 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036050.pdf [firstpage_image] =>[orig_patent_app_number] => 11880753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/880753
Package with solder-filled via holes in molding layers Jul 22, 2007 Issued
Array ( [id] => 163250 [patent_doc_number] => 07671456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Power management integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/825252 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671456.pdf [firstpage_image] =>[orig_patent_app_number] => 11825252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/825252
Power management integrated circuit Jul 2, 2007 Issued
Array ( [id] => 243625 [patent_doc_number] => 07589362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Configurable non-volatile logic structure for characterizing an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/764157 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14458 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589362.pdf [firstpage_image] =>[orig_patent_app_number] => 11764157 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764157
Configurable non-volatile logic structure for characterizing an integrated circuit device Jun 14, 2007 Issued
Array ( [id] => 4564161 [patent_doc_number] => 07846750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Textured rear electrode structure for use in photovoltaic device such as CIGS/CIS solar cell' [patent_app_type] => utility [patent_app_number] => 11/808764 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6600 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846750.pdf [firstpage_image] =>[orig_patent_app_number] => 11808764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808764
Textured rear electrode structure for use in photovoltaic device such as CIGS/CIS solar cell Jun 11, 2007 Issued
Array ( [id] => 5016278 [patent_doc_number] => 20070259487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Method of forming a polysilicon film and method of manufacturing a thin film transistor including a polysilicon film' [patent_app_type] => utility [patent_app_number] => 11/808521 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6071 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259487.pdf [firstpage_image] =>[orig_patent_app_number] => 11808521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808521
Method of forming a polysilicon film and method of manufacturing a thin film transistor including a polysilicon film Jun 10, 2007 Issued
Array ( [id] => 263709 [patent_doc_number] => 07569473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Methods of forming semiconductor assemblies' [patent_app_type] => utility [patent_app_number] => 11/760458 [patent_app_country] => US [patent_app_date] => 2007-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569473.pdf [firstpage_image] =>[orig_patent_app_number] => 11760458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760458
Methods of forming semiconductor assemblies Jun 7, 2007 Issued
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