Search

Neeraj Sharma

Examiner (ID: 18407, Phone: (571)270-5487 , Office: P/2659 )

Most Active Art Unit
2659
Art Unit(s)
2626, 2659
Total Applications
576
Issued Applications
473
Pending Applications
47
Abandoned Applications
71

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20590666 [patent_doc_number] => 20260076267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => 3D INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 19/384467 [patent_app_country] => US [patent_app_date] => 2025-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19384467 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/384467
3D INTEGRATED CIRCUIT PACKAGE Nov 9, 2025 Pending
Array ( [id] => 20224683 [patent_doc_number] => 20250287614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 19/214066 [patent_app_country] => US [patent_app_date] => 2025-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19214066 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/214066
COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE May 20, 2025 Pending
Array ( [id] => 19688147 [patent_doc_number] => 20250006692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Method for Packaging Stacking Flip Chip [patent_app_type] => utility [patent_app_number] => 18/884085 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/884085
Method for packaging stacking flip chip Sep 11, 2024 Issued
Array ( [id] => 20532341 [patent_doc_number] => 12550796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Electronic package and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 18/826815 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826815
Electronic package and fabricating method thereof Sep 5, 2024 Issued
Array ( [id] => 20153369 [patent_doc_number] => 20250253207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => FABRICATION METHODS AND STRUCTURES FOR LIQUID COOLING CHANNEL CHIP [patent_app_type] => utility [patent_app_number] => 18/788853 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788853
FABRICATION METHODS AND STRUCTURES FOR LIQUID COOLING CHANNEL CHIP Jul 29, 2024 Pending
Array ( [id] => 19546547 [patent_doc_number] => 20240363583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHODS OF FORMING WIRE INTERCONNECT STRUCTURES AND RELATED WIRE BONDING TOOLS [patent_app_type] => utility [patent_app_number] => 18/765653 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765653
Methods of forming wire interconnect structures and related wire bonding tools Jul 7, 2024 Issued
Array ( [id] => 19500379 [patent_doc_number] => 20240339397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => INTERCONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/746055 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746055
Interconnection structure Jun 17, 2024 Issued
Array ( [id] => 19500342 [patent_doc_number] => 20240339360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES [patent_app_type] => utility [patent_app_number] => 18/744493 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744493
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES Jun 13, 2024 Abandoned
Array ( [id] => 19484290 [patent_doc_number] => 20240332332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => TRENCH ISOLATION STRUCTURE FOR SCALED PIXEL REGION [patent_app_type] => utility [patent_app_number] => 18/733947 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733947
TRENCH ISOLATION STRUCTURE FOR SCALED PIXEL REGION Jun 4, 2024 Pending
Array ( [id] => 19436082 [patent_doc_number] => 20240304580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => BONDING STRUCTURE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/663124 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663124
BONDING STRUCTURE AND METHOD THEREOF May 13, 2024 Pending
Array ( [id] => 20553296 [patent_doc_number] => 12564111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Double-sided integrated circuit module having an exposed semiconductor die [patent_app_type] => utility [patent_app_number] => 18/657968 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657968
Double-sided integrated circuit module having an exposed semiconductor die May 7, 2024 Issued
Array ( [id] => 19421019 [patent_doc_number] => 20240297143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => BONDING TOOL AND BONDING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/654016 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654016
Bonding tool and bonding method thereof May 2, 2024 Issued
Array ( [id] => 19407295 [patent_doc_number] => 20240290806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ABSORPTION ENHANCEMENT STRUCTURE TO INCREASE QUANTUM EFFICIENCY OF IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 18/650172 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650172
Absorption enhancement structure to increase quantum efficiency of image sensor Apr 29, 2024 Issued
Array ( [id] => 19384767 [patent_doc_number] => 20240274637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/643860 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643860
Image sensor device and manufacturing method thereof Apr 22, 2024 Issued
Array ( [id] => 20532315 [patent_doc_number] => 12550769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Method for forming a package structure [patent_app_type] => utility [patent_app_number] => 18/602185 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602185
Method for forming a package structure Mar 11, 2024 Issued
Array ( [id] => 19399745 [patent_doc_number] => 12074133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-27 [patent_title] => Chip bonding apparatus and securing assembly therefor [patent_app_type] => utility [patent_app_number] => 18/597172 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597172
Chip bonding apparatus and securing assembly therefor Mar 5, 2024 Issued
Array ( [id] => 19269467 [patent_doc_number] => 20240213171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/596488 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596488
Ultra small molded module integrated with die by module-on-wafer assembly Mar 4, 2024 Issued
Array ( [id] => 19705097 [patent_doc_number] => 12199145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Epitaxial structure and transistor including the same [patent_app_type] => utility [patent_app_number] => 18/591803 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591803
Epitaxial structure and transistor including the same Feb 28, 2024 Issued
Array ( [id] => 19237442 [patent_doc_number] => 20240194637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => WAFER BONDING APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/582381 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582381
Wafer bonding apparatus and method Feb 19, 2024 Issued
Array ( [id] => 20153384 [patent_doc_number] => 20250253222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/430507 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430507
SEMICONDUCTOR DEVICE Jan 31, 2024 Pending
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