Search

Neil Abrams

Examiner (ID: 6852, Phone: (571)272-2089 , Office: P/2831 )

Most Active Art Unit
3202
Art Unit(s)
2839, 2833, 2832, 3205, 2834, 2831, 3202, 1611
Total Applications
3845
Issued Applications
3190
Pending Applications
146
Abandoned Applications
527

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19733574 [patent_doc_number] => 12211574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Method for error correction coding with multiple hash groupings and device for performing the same [patent_app_type] => utility [patent_app_number] => 18/121168 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121168
Method for error correction coding with multiple hash groupings and device for performing the same Mar 13, 2023 Issued
Array ( [id] => 18812250 [patent_doc_number] => 20230386587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAM OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/113617 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113617
Memory device, memory system, and program operation method thereof Feb 22, 2023 Issued
Array ( [id] => 19356729 [patent_doc_number] => 12057184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Memory systems having memory devices therein with enhanced error correction capability and methods of operating same [patent_app_type] => utility [patent_app_number] => 18/164100 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 9120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164100
Memory systems having memory devices therein with enhanced error correction capability and methods of operating same Feb 2, 2023 Issued
Array ( [id] => 18423663 [patent_doc_number] => 20230178127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => DUAL-ADDRESS COMMAND MANAGEMENT USING CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 18/105337 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105337 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105337
Dual-address command management using content addressable memory Feb 2, 2023 Issued
Array ( [id] => 18865568 [patent_doc_number] => 20230420005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => RANDOM DATA GENERATION CIRCUIT AND READ/WRITE TRAINING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/093728 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093728
Random data generation circuit and read/write training circuit Jan 4, 2023 Issued
Array ( [id] => 19733564 [patent_doc_number] => 12211564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Memory device, method for programming memory device, program verification method and memory system [patent_app_type] => utility [patent_app_number] => 18/091231 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 17635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091231
Memory device, method for programming memory device, program verification method and memory system Dec 28, 2022 Issued
Array ( [id] => 18351416 [patent_doc_number] => 20230139527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/089703 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089703
Semiconductor device, electronic component, and electronic device Dec 27, 2022 Issued
Array ( [id] => 19205883 [patent_doc_number] => 20240177782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => STATIC RANDOM ACCESS MEMORY APPARATUS THAT MAINTAINS STABLE WRITE PERFORMANCE IN LOW POWER ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/146167 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146167
Static random access memory apparatus that maintains stable write performance in low power environment Dec 22, 2022 Issued
Array ( [id] => 19269066 [patent_doc_number] => 20240212770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ONE-TIME PROGRAMMABLE FUSE USING THIN FILM RESISTOR LAYER, AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 18/145341 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145341
One-time programmable fuse using thin film resistor layer, and related method Dec 21, 2022 Issued
Array ( [id] => 19596797 [patent_doc_number] => 12154650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Electronic device and power control method thereof [patent_app_type] => utility [patent_app_number] => 18/084902 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3843 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084902
Electronic device and power control method thereof Dec 19, 2022 Issued
Array ( [id] => 18623579 [patent_doc_number] => 11756632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/084363 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 21415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084363
Semiconductor memory device Dec 18, 2022 Issued
Array ( [id] => 19654256 [patent_doc_number] => 12176056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor device configured to store parity data and method of operating the semiconductor device [patent_app_type] => utility [patent_app_number] => 18/075003 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 11404 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075003
Semiconductor device configured to store parity data and method of operating the semiconductor device Dec 4, 2022 Issued
Array ( [id] => 19223742 [patent_doc_number] => 20240188446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MRAM DEVICE WITH WRAP-AROUND TOP ELECTRODE [patent_app_type] => utility [patent_app_number] => 18/061491 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061491
MRAM device with wrap-around top electrode Dec 4, 2022 Issued
Array ( [id] => 19022906 [patent_doc_number] => 20240079077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE FOR PERFORMING DEFECTIVE ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/070606 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070606
Semiconductor system including semiconductor device for performing defective analysis Nov 28, 2022 Issued
Array ( [id] => 18379423 [patent_doc_number] => 20230154512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY TOPOLOGIES [patent_app_type] => utility [patent_app_number] => 17/994848 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994848
Memory topologies Nov 27, 2022 Issued
Array ( [id] => 18213326 [patent_doc_number] => 20230059590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/982955 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982955
Magnetic tunneling junction device and memory device including the same Nov 7, 2022 Issued
Array ( [id] => 19796084 [patent_doc_number] => 12237049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor memory devices having efficient serializers therein for transferring data [patent_app_type] => utility [patent_app_number] => 18/052976 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10456 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052976
Semiconductor memory devices having efficient serializers therein for transferring data Nov 6, 2022 Issued
Array ( [id] => 19160840 [patent_doc_number] => 20240153547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => CONTROL METHOD AND SYSTEM IN 3D NAND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/052777 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052777
Control method and system in 3D NAND systems Nov 3, 2022 Issued
Array ( [id] => 18345348 [patent_doc_number] => 20230133458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MEMORY CONTROLLER, CONTROL METHOD FOR MEMORY CONTROLLER, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/051811 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051811
Memory controller, control method for memory controller, and storage medium Oct 31, 2022 Issued
Array ( [id] => 19733577 [patent_doc_number] => 12211577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Layout for dual in-line memory to support 128-byte cache line processor [patent_app_type] => utility [patent_app_number] => 18/048911 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048911
Layout for dual in-line memory to support 128-byte cache line processor Oct 23, 2022 Issued
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