Search

Neil Abrams

Examiner (ID: 6852, Phone: (571)272-2089 , Office: P/2831 )

Most Active Art Unit
3202
Art Unit(s)
2839, 2833, 2832, 3205, 2834, 2831, 3202, 1611
Total Applications
3845
Issued Applications
3190
Pending Applications
146
Abandoned Applications
527

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18338000 [patent_doc_number] => 20230129949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MEMORY DEVICE PERFORMING OFFSET CALIBRATION AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/968052 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968052
Memory device performing offset calibration and operating method thereof Oct 17, 2022 Issued
Array ( [id] => 18394546 [patent_doc_number] => 20230162767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MODIFICATION OF A COMMAND TIMING PATTERN [patent_app_type] => utility [patent_app_number] => 17/938002 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/938002
Modification of a command timing pattern Oct 3, 2022 Issued
Array ( [id] => 18874473 [patent_doc_number] => 11862294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Memory subsystem register clock driver clock teeing [patent_app_type] => utility [patent_app_number] => 17/936048 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936048
Memory subsystem register clock driver clock teeing Sep 27, 2022 Issued
Array ( [id] => 19314221 [patent_doc_number] => 12040045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor device performing training operation and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/950292 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950292
Semiconductor device performing training operation and operating method thereof Sep 21, 2022 Issued
Array ( [id] => 18162410 [patent_doc_number] => 20230029003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIME [patent_app_type] => utility [patent_app_number] => 17/949836 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949836 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949836
Memory with programmable refresh order and stagger time Sep 20, 2022 Issued
Array ( [id] => 19427963 [patent_doc_number] => 12087391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Drift compensation for codewords in memory [patent_app_type] => utility [patent_app_number] => 17/948423 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6509 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17948423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/948423
Drift compensation for codewords in memory Sep 19, 2022 Issued
Array ( [id] => 18500275 [patent_doc_number] => 20230223060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/939016 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939016
Semiconductor device Sep 6, 2022 Issued
Array ( [id] => 18147344 [patent_doc_number] => 20230021201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/939908 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939908
Apparatus with data-rate-based voltage control mechanism and methods for operating the same Sep 6, 2022 Issued
Array ( [id] => 18661039 [patent_doc_number] => 20230307052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/901239 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901239
Semiconductor storage device Aug 31, 2022 Issued
Array ( [id] => 19664440 [patent_doc_number] => 12178148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Storage device [patent_app_type] => utility [patent_app_number] => 17/899914 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 6801 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899914
Storage device Aug 30, 2022 Issued
Array ( [id] => 19765697 [patent_doc_number] => 12223995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Adaptive memory registers [patent_app_type] => utility [patent_app_number] => 17/823407 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19069 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823407
Adaptive memory registers Aug 29, 2022 Issued
Array ( [id] => 19376456 [patent_doc_number] => 12068034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming [patent_app_type] => utility [patent_app_number] => 17/899409 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899409
Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming Aug 29, 2022 Issued
Array ( [id] => 18890794 [patent_doc_number] => 11869571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same [patent_app_type] => utility [patent_app_number] => 17/899141 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899141
Memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same Aug 29, 2022 Issued
Array ( [id] => 18990862 [patent_doc_number] => 20240062831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/891072 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891072
Memory device and read operation during suspension of program operation thereof Aug 17, 2022 Issued
Array ( [id] => 18257994 [patent_doc_number] => 20230085034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MEMORY ARRAY STRUCTURES HAVING MULTIPLE SUB-BLOCKS, APPARATUS CONTAINING SUCH MEMORY ARRAY STRUCTURES, AND OPERATION OF SUCH APPARATUS [patent_app_type] => utility [patent_app_number] => 17/889471 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -49 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889471
Apparatus containing memory array structures having multiple sub-blocks Aug 16, 2022 Issued
Array ( [id] => 18061468 [patent_doc_number] => 20220392554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ADJUSTING PASS-THROUGH VOLTAGE BASED ON THRESHOLD VOLTAGE SHIFT [patent_app_type] => utility [patent_app_number] => 17/889863 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889863
Adjusting pass-through voltage based on threshold voltage shift Aug 16, 2022 Issued
Array ( [id] => 18973809 [patent_doc_number] => 20240053901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/888080 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888080
Adaptive bitline voltage for memory operations Aug 14, 2022 Issued
Array ( [id] => 18362775 [patent_doc_number] => 20230144366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/876046 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876046
Volatile memory device Jul 27, 2022 Issued
Array ( [id] => 18874471 [patent_doc_number] => 11862292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Buffer control of multiple memory banks [patent_app_type] => utility [patent_app_number] => 17/876142 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876142
Buffer control of multiple memory banks Jul 27, 2022 Issued
Array ( [id] => 19294345 [patent_doc_number] => 12033706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Method of operating nonvolatile memory device, nonvolatile memory device and memory controller performing the same [patent_app_type] => utility [patent_app_number] => 17/873739 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 19306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873739
Method of operating nonvolatile memory device, nonvolatile memory device and memory controller performing the same Jul 25, 2022 Issued
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