Nelson M. Rosario

Array ( [id] => 19933578 [patent_doc_number] => 12306782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Peer arrangements among switch-coupled endpoint devices [patent_app_type] => utility [patent_app_number] => 18/741282 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19756633 [patent_doc_number] => 20250045198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => ACCELERATING COMMAND LATENCIES USING A HYBRID COMPUTE EXPRESS LINK TYPE-3 SSD MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/678973 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19450893 [patent_doc_number] => 20240311023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DATA STORAGE DEVICE WITH NOISE INJECTION [patent_app_type] => utility [patent_app_number] => 18/670512 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20310716 [patent_doc_number] => 20250328345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => SYSTEM-INTEGRATED SOLUTION FOR IO DEVICE EXTENDED CONTROL WITHOUT OPERATING SYSTEM DRIVER INVOLVEMENT [patent_app_type] => utility [patent_app_number] => 18/642379 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20290151 [patent_doc_number] => 20250315394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SECURE, SCALABLE DOORBELL MECHANISM BETWEEN PEERS IN A PCIE FABRIC [patent_app_type] => utility [patent_app_number] => 18/630387 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19320097 [patent_doc_number] => 20240241641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/618966 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19391271 [patent_doc_number] => 20240281141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES [patent_app_type] => utility [patent_app_number] => 18/443956 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19383178 [patent_doc_number] => 20240273048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DATA OPERATION SYSTEM, DATA OPERATION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/442637 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19451138 [patent_doc_number] => 20240311268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => CONTROL PROGRAM, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/439857 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19419866 [patent_doc_number] => 20240295989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => NONVOLATILE MEMORY PACKAGE, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/538512 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19819256 [patent_doc_number] => 20250077463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => RESERVATION OF PCIe SLOTS FOR MANAGEMENT BY A RAID DRIVER [patent_app_type] => utility [patent_app_number] => 18/527579 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19267449 [patent_doc_number] => 20240211152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DISTRIBUTED MEMORY DATA PATH FOR CIRCUIT UNDER ARRAY [patent_app_type] => utility [patent_app_number] => 18/524739 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19994914 [patent_doc_number] => 20250133136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Remote Memory Filling [patent_app_type] => utility [patent_app_number] => 18/491820 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19994912 [patent_doc_number] => 20250133134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => METHOD AND SYSTEM FOR SCALABLE RELIABLE CONNECTION TRANSPORT FOR RDMA [patent_app_type] => utility [patent_app_number] => 18/489110 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19084729 [patent_doc_number] => 20240111530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/243264 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18863927 [patent_doc_number] => 20230418363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => CARD AND HOST APPARATUS [patent_app_type] => utility [patent_app_number] => 18/462493 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787393 [patent_doc_number] => 20250061072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => HDMI display control [patent_app_type] => utility [patent_app_number] => 18/451169 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18973998 [patent_doc_number] => 20240054090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SYSTEM FOR OVERLAY CONFIGURATION OF A DATACENTER NETWORK [patent_app_type] => utility [patent_app_number] => 18/232218 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215129 [patent_doc_number] => 12411782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Apparatus and method for configuring sets of interrupts [patent_app_type] => utility [patent_app_number] => 18/218119 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19688965 [patent_doc_number] => 20250007510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => CONFIGURABLE TRAFFIC CONTROL CIRCUITS IN MESH NETWORK NODES TO MITIGATE VOLTAGE DROOP AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/216974 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216974 [rel_patent_id] =>[rel_patent_doc_number] =>)