Search

Nelson Y. Garces

Examiner (ID: 885, Phone: (571)272-8249 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
694
Issued Applications
533
Pending Applications
93
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19486628 [patent_doc_number] => 20240334670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Non-Interleaving N-Well And P-Well Pickup Region Design For Ic Devices [patent_app_type] => utility [patent_app_number] => 18/741463 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741463
Non-interleaving N-well and P-well pickup region design for IC devices Jun 11, 2024 Issued
Array ( [id] => 20307105 [patent_doc_number] => 12453116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Transistors with stacked channels and the methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/734635 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 63 [patent_no_of_words] => 4116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734635
Transistors with stacked channels and the methods of forming the same Jun 4, 2024 Issued
Array ( [id] => 19452883 [patent_doc_number] => 20240313013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/676161 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676161
SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF May 27, 2024 Pending
Array ( [id] => 19452883 [patent_doc_number] => 20240313013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/676161 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676161
SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF May 27, 2024 Pending
Array ( [id] => 19351284 [patent_doc_number] => 20240260248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => FIN-BASED WELL STRAPS FOR IMPROVING MEMORY MACRO PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/608045 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608045
FIN-BASED WELL STRAPS FOR IMPROVING MEMORY MACRO PERFORMANCE Mar 17, 2024 Pending
Array ( [id] => 19251429 [patent_doc_number] => 20240202420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED CIRCUIT WITH DUMMY BOUNDARY CELLS [patent_app_type] => utility [patent_app_number] => 18/589569 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589569
INTEGRATED CIRCUIT WITH DUMMY BOUNDARY CELLS Feb 27, 2024 Pending
Array ( [id] => 20161372 [patent_doc_number] => 12388007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Capacitor networks for harmonic control in power devices [patent_app_type] => utility [patent_app_number] => 18/582162 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582162
Capacitor networks for harmonic control in power devices Feb 19, 2024 Issued
Array ( [id] => 19206422 [patent_doc_number] => 20240178321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Fin Field-Effect Transistor Device with Composite Liner for the Fin [patent_app_type] => utility [patent_app_number] => 18/413716 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413716
Fin field-effect transistor device with composite liner for the fin Jan 15, 2024 Issued
Array ( [id] => 19206422 [patent_doc_number] => 20240178321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => Fin Field-Effect Transistor Device with Composite Liner for the Fin [patent_app_type] => utility [patent_app_number] => 18/413716 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413716
Fin field-effect transistor device with composite liner for the fin Jan 15, 2024 Issued
Array ( [id] => 19101122 [patent_doc_number] => 20240120350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => GEIGER-MODE FOCAL PLANE ARRAY WITH MONOLITHICALLY INTEGRATED RESISTORS [patent_app_type] => utility [patent_app_number] => 18/391093 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/391093
GEIGER-MODE FOCAL PLANE ARRAY WITH MONOLITHICALLY INTEGRATED RESISTORS Dec 19, 2023 Pending
Array ( [id] => 19054742 [patent_doc_number] => 20240096711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/522867 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522867
METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES Nov 28, 2023 Pending
Array ( [id] => 19733868 [patent_doc_number] => 12211870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Fingerprint sensor, method for manufacturing fingerprint sensor, and display device including fingerprint sensor [patent_app_type] => utility [patent_app_number] => 18/384916 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12101 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384916
Fingerprint sensor, method for manufacturing fingerprint sensor, and display device including fingerprint sensor Oct 29, 2023 Issued
Array ( [id] => 19868670 [patent_doc_number] => 20250107456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => CONTACTS FOR JOSEPHSON JUNCTION-BASED QUBITS [patent_app_type] => utility [patent_app_number] => 18/475476 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475476
CONTACTS FOR JOSEPHSON JUNCTION-BASED QUBITS Sep 26, 2023 Pending
Array ( [id] => 19866385 [patent_doc_number] => 20250105171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS [patent_app_type] => utility [patent_app_number] => 18/475419 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475419 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475419
INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS Sep 26, 2023 Pending
Array ( [id] => 19850796 [patent_doc_number] => 20250096147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => OVERLAY MARK [patent_app_type] => utility [patent_app_number] => 18/470421 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470421
OVERLAY MARK Sep 19, 2023 Pending
Array ( [id] => 19850796 [patent_doc_number] => 20250096147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => OVERLAY MARK [patent_app_type] => utility [patent_app_number] => 18/470421 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470421
OVERLAY MARK Sep 19, 2023 Pending
Array ( [id] => 19727154 [patent_doc_number] => 20250029905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => STRUCTURE OF CHIP PACKAGE INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/470409 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470409
STRUCTURE OF CHIP PACKAGE INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF Sep 18, 2023 Pending
Array ( [id] => 19193633 [patent_doc_number] => 20240172546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DISPLAY PANEL, THIN FILM TRANSISTOR INCLUDED IN THE SAME, AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/470254 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470254
DISPLAY PANEL, THIN FILM TRANSISTOR INCLUDED IN THE SAME, AND MANUFACTURING METHOD OF THE SAME Sep 18, 2023 Pending
Array ( [id] => 19885829 [patent_doc_number] => 12271545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Display device having fracture resistance [patent_app_type] => utility [patent_app_number] => 18/369814 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 13338 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369814
Display device having fracture resistance Sep 17, 2023 Issued
Array ( [id] => 19255162 [patent_doc_number] => 20240206159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/454105 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454105
INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME Aug 22, 2023 Pending
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