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Nelson Y. Garces

Examiner (ID: 16254, Phone: (571)272-8249 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
741
Issued Applications
558
Pending Applications
88
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20792796 [patent_doc_number] => 12666728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2026-06-23 [patent_title] => Monolithic focal plane array circuit and method thereof [patent_app_type] => utility [patent_app_number] => 18/483922 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 121 [patent_no_of_words] => 7473 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483922
Monolithic focal plane array circuit and method thereof Oct 9, 2023 Issued
Array ( [id] => 18940013 [patent_doc_number] => 20240035152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => METHODS FOR DEPOSITING MOLYBDENUM SULFIDE [patent_app_type] => utility [patent_app_number] => 18/378425 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378425 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378425
METHODS FOR DEPOSITING MOLYBDENUM SULFIDE Oct 9, 2023 Pending
Array ( [id] => 18906084 [patent_doc_number] => 20240021569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 18/477635 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477635
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE Sep 28, 2023 Pending
Array ( [id] => 19868670 [patent_doc_number] => 20250107456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => CONTACTS FOR JOSEPHSON JUNCTION-BASED QUBITS [patent_app_type] => utility [patent_app_number] => 18/475476 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475476 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475476
CONTACTS FOR JOSEPHSON JUNCTION-BASED QUBITS Sep 26, 2023 Pending
Array ( [id] => 19866318 [patent_doc_number] => 20250105104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => QUAD FLAT NO-LEAD PACKAGE WITH ENHANCED CORNER PADS FOR BOARD LEVEL RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/475563 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475563
QUAD FLAT NO-LEAD PACKAGE WITH ENHANCED CORNER PADS FOR BOARD LEVEL RELIABILITY Sep 26, 2023 Pending
Array ( [id] => 19866385 [patent_doc_number] => 20250105171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS [patent_app_type] => utility [patent_app_number] => 18/475419 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475419 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475419
Integrated circuit with dielectric layer having selectively implanted stress-setting dopants Sep 26, 2023 Issued
Array ( [id] => 18907913 [patent_doc_number] => 20240023398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/475543 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475543
Display panel and display apparatus including the display panel Sep 26, 2023 Issued
Array ( [id] => 18906238 [patent_doc_number] => 20240021723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/475675 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 527 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475675 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475675
Silicon carbide semiconductor device Sep 26, 2023 Issued
Array ( [id] => 19866310 [patent_doc_number] => 20250105096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SYSTEMS AND METHODS FOR POWER DELIVERY FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/475566 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475566
SYSTEMS AND METHODS FOR POWER DELIVERY FOR SEMICONDUCTOR DEVICES Sep 26, 2023 Pending
Array ( [id] => 19850796 [patent_doc_number] => 20250096147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => OVERLAY MARK [patent_app_type] => utility [patent_app_number] => 18/470421 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470421
OVERLAY MARK Sep 19, 2023 Pending
Array ( [id] => 20853324 [patent_doc_number] => 12690379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-21 [patent_title] => Display panel and thin film transistor including a control electrode comprising molybdenum, nitrogen and chlorine [patent_app_type] => utility [patent_app_number] => 18/470254 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7138 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470254
DISPLAY PANEL, THIN FILM TRANSISTOR INCLUDED IN THE SAME, AND MANUFACTURING METHOD OF THE SAME Sep 18, 2023 Issued
Array ( [id] => 19727154 [patent_doc_number] => 20250029905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => STRUCTURE OF CHIP PACKAGE INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/470409 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470409
STRUCTURE OF CHIP PACKAGE INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF Sep 18, 2023 Pending
Array ( [id] => 19850740 [patent_doc_number] => 20250096091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PACKAGE COMPRISING A SUBSTRATE WITH VIA INTERCONNECT WITH VERTICAL WALLS [patent_app_type] => utility [patent_app_number] => 18/470250 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470250
PACKAGE COMPRISING A SUBSTRATE WITH VIA INTERCONNECT WITH VERTICAL WALLS Sep 18, 2023 Pending
Array ( [id] => 19885829 [patent_doc_number] => 12271545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Display device having fracture resistance [patent_app_type] => utility [patent_app_number] => 18/369814 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 13338 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369814
Display device having fracture resistance Sep 17, 2023 Issued
Array ( [id] => 20691882 [patent_doc_number] => 12622054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Integration of multimodal transistors with transistor fabrication sequence [patent_app_type] => utility [patent_app_number] => 18/244423 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 7046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18244423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/244423
Integration of multimodal transistors with transistor fabrication sequence Sep 10, 2023 Issued
Array ( [id] => 19823371 [patent_doc_number] => 20250081578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => SEMICONDUCTOR DEVICE WITH CONDUCTIVE FEATURE CONNECTING TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/459448 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459448
SEMICONDUCTOR DEVICE WITH CONDUCTIVE FEATURE CONNECTING TRANSISTORS Aug 31, 2023 Pending
Array ( [id] => 19255162 [patent_doc_number] => 20240206159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/454105 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454105
INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME Aug 22, 2023 Pending
Array ( [id] => 19024873 [patent_doc_number] => 20240081044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/450731 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450731
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Aug 15, 2023 Pending
Array ( [id] => 20361812 [patent_doc_number] => 12477831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor device having interleaved clock gate blocks and decoupling capacitor blocks and method of operating same [patent_app_type] => utility [patent_app_number] => 18/447857 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 10595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447857
Semiconductor device having interleaved clock gate blocks and decoupling capacitor blocks and method of operating same Aug 9, 2023 Issued
Array ( [id] => 18812816 [patent_doc_number] => 20230387153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => PIXEL SENSOR INCLUDING A LAYER STACK [patent_app_type] => utility [patent_app_number] => 18/446707 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446707
PIXEL SENSOR INCLUDING A LAYER STACK Aug 8, 2023 Pending
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