Nelson Y. Garces

Array ( [id] => 18929275 [patent_doc_number] => 20240032279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 18/150775 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19524095 [patent_doc_number] => 12125835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Module package with high illumination efficiency [patent_app_type] => utility [patent_app_number] => 18/083619 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3341 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18334650 [patent_doc_number] => 20230126598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => Attachment of Stress Sensitive Integrated Circuit Dies [patent_app_type] => utility [patent_app_number] => 18/064705 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19507953 [patent_doc_number] => 12119384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Semiconductor device having conductive field plate overlapping an edge of an active region [patent_app_type] => utility [patent_app_number] => 18/059701 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 6576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18272138 [patent_doc_number] => 20230093380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/070303 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18835317 [patent_doc_number] => 20230403844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/993473 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18254671 [patent_doc_number] => 20230081710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => Isolation Structures [patent_app_type] => utility [patent_app_number] => 18/057688 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19176258 [patent_doc_number] => 20240162232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REGIONS [patent_app_type] => utility [patent_app_number] => 17/985861 [patent_app_country] => US [patent_app_date] => 2022-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19176258 [patent_doc_number] => 20240162232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => INTEGRATED STRUCTURE WITH TRAP RICH REGIONS AND LOW RESISTIVITY REGIONS [patent_app_type] => utility [patent_app_number] => 17/985861 [patent_app_country] => US [patent_app_date] => 2022-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19444605 [patent_doc_number] => 12094896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Photosensitive semiconductor device including heterojunction photodiode [patent_app_type] => utility [patent_app_number] => 17/984261 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3935 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18239100 [patent_doc_number] => 20230071411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => PHOTOSENSITIVE SEMICONDUCTOR DEVICE INCLUDING HETEROJUNCTION PHOTODIODE [patent_app_type] => utility [patent_app_number] => 17/984243 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19148581 [patent_doc_number] => 20240147699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICE HAVING WORD LINE EMBEDDED IN GATE TRENCH [patent_app_type] => utility [patent_app_number] => 18/051690 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19086146 [patent_doc_number] => 20240112947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SHALLOW TRENCH ISOLATION (STI) PROCESSING WITH LOCAL OXIDATION OF SILICON (LOCOS) [patent_app_type] => utility [patent_app_number] => 17/977250 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18335109 [patent_doc_number] => 20230127057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => PIXELATED FILTER [patent_app_type] => utility [patent_app_number] => 17/972937 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18335109 [patent_doc_number] => 20230127057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => PIXELATED FILTER [patent_app_type] => utility [patent_app_number] => 17/972937 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19414866 [patent_doc_number] => 12080703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Semiconductor cell blocks having non-integer multiple of cell heights [patent_app_type] => utility [patent_app_number] => 18/048186 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6164 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18221811 [patent_doc_number] => 20230060805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/046149 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18167326 [patent_doc_number] => 20230033933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => IMAGING ELEMENT HAVING P-TYPE AND N-TYPE SOLID PHASE DIFFUSION LAYERS FORMED IN A SIDE WALL OF AN INTERPIXEL LIGHT SHIELDING WALL [patent_app_type] => utility [patent_app_number] => 17/962262 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19086341 [patent_doc_number] => 20240113142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/958035 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19781525 [patent_doc_number] => 12230563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Method to enable 30 microns pitch EMIB or below [patent_app_type] => utility [patent_app_number] => 17/956769 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5635 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956769 [rel_patent_id] =>[rel_patent_doc_number] =>)