Search

Nelson Y. Garces

Examiner (ID: 885, Phone: (571)272-8249 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
694
Issued Applications
533
Pending Applications
93
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18961124 [patent_doc_number] => 20240049451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/879971 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879971
Semiconductor structure and method of manufacturing the same including buried word lines of different widths Aug 2, 2022 Issued
Array ( [id] => 18008714 [patent_doc_number] => 20220367481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Fin-Based Well Straps For Improving Memory Macro Performance [patent_app_type] => utility [patent_app_number] => 17/874463 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874463
Fin-based well straps for improving memory macro performance Jul 26, 2022 Issued
Array ( [id] => 19062102 [patent_doc_number] => 11941338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Integrated circuit with dummy boundary cells [patent_app_type] => utility [patent_app_number] => 17/873699 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 8314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873699
Integrated circuit with dummy boundary cells Jul 25, 2022 Issued
Array ( [id] => 18024670 [patent_doc_number] => 20220376169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Structure and Method for an MRAM Device with a Multi-Layer Top Electrode [patent_app_type] => utility [patent_app_number] => 17/814917 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814917
Structure and method for an MRAM device with a multi-layer top electrode Jul 25, 2022 Issued
Array ( [id] => 18241279 [patent_doc_number] => 20230073590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/814517 [patent_app_country] => US [patent_app_date] => 2022-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814517
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Jul 23, 2022 Pending
Array ( [id] => 18024444 [patent_doc_number] => 20220375943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Non-Interleaving N-Well And P-Well Pickup Region Design For Ic Devices [patent_app_type] => utility [patent_app_number] => 17/871603 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871603
Non-interleaving N-well and P-well pickup region design for IC devices Jul 21, 2022 Issued
Array ( [id] => 18008900 [patent_doc_number] => 20220367667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Contact with a Silicide Region [patent_app_type] => utility [patent_app_number] => 17/869521 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869521
Contact with a silicide region Jul 19, 2022 Issued
Array ( [id] => 18008900 [patent_doc_number] => 20220367667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Contact with a Silicide Region [patent_app_type] => utility [patent_app_number] => 17/869521 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869521
Contact with a silicide region Jul 19, 2022 Issued
Array ( [id] => 17993237 [patent_doc_number] => 20220359274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Method and Apparatus for Back End of Line Semiconductor Device Processing [patent_app_type] => utility [patent_app_number] => 17/869177 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869177
Interconnect line for semiconductor device Jul 19, 2022 Issued
Array ( [id] => 18161321 [patent_doc_number] => 20230027913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => METHOD FOR FORMING TRANSISTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/813656 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813656
METHOD FOR FORMING TRANSISTOR STRUCTURE Jul 19, 2022 Pending
Array ( [id] => 18320148 [patent_doc_number] => 20230118276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/869206 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869206
Semiconductor device including air gap structure above word line Jul 19, 2022 Issued
Array ( [id] => 18182076 [patent_doc_number] => 20230042805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/813817 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813817
RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME Jul 19, 2022 Abandoned
Array ( [id] => 19487180 [patent_doc_number] => 12106904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Semiconductor device with a booster layer and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/860367 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 63 [patent_no_of_words] => 28627 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860367
Semiconductor device with a booster layer and method for fabricating the same Jul 7, 2022 Issued
Array ( [id] => 18167711 [patent_doc_number] => 20230034318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => BIOMETRIC IDENTIFICATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/860132 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860132
BIOMETRIC IDENTIFICATION DEVICE Jul 7, 2022 Issued
Array ( [id] => 17963767 [patent_doc_number] => 20220344348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/858084 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858084
Dynamic random access memory having word line buried in chop structure with different widths Jul 5, 2022 Issued
Array ( [id] => 20230440 [patent_doc_number] => 12419105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Protection ring, method for forming protection ring, and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/851673 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851673
Protection ring, method for forming protection ring, and semiconductor structure Jun 27, 2022 Issued
Array ( [id] => 20230440 [patent_doc_number] => 12419105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Protection ring, method for forming protection ring, and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/851673 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851673
Protection ring, method for forming protection ring, and semiconductor structure Jun 27, 2022 Issued
Array ( [id] => 19277459 [patent_doc_number] => 12027592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Method of manufacturing a heterostructure or a stacked semiconductor structure having a silicon-germanium interface [patent_app_type] => utility [patent_app_number] => 17/850310 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 9594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850310
Method of manufacturing a heterostructure or a stacked semiconductor structure having a silicon-germanium interface Jun 26, 2022 Issued
Array ( [id] => 19399680 [patent_doc_number] => 12074066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Integrated circuit component with conductive terminals of different dimensions and package structure having the same [patent_app_type] => utility [patent_app_number] => 17/846021 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 10992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846021
Integrated circuit component with conductive terminals of different dimensions and package structure having the same Jun 21, 2022 Issued
Array ( [id] => 18868024 [patent_doc_number] => 20230422461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => DECOUPLING CAPACITOR INSIDE GATE CUT TRENCH [patent_app_type] => utility [patent_app_number] => 17/808178 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808178
Decoupling capacitor inside gate cut trench Jun 21, 2022 Issued
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