
Nema O. Berezny
Examiner (ID: 9201)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 286 |
| Issued Applications | 250 |
| Pending Applications | 5 |
| Abandoned Applications | 31 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 944108
[patent_doc_number] => 06967162
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-22
[patent_title] => 'Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding'
[patent_app_type] => utility
[patent_app_number] => 10/988769
[patent_app_country] => US
[patent_app_date] => 2004-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2083
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[patent_words_short_claim] => 52
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/967/06967162.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988769
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988769 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding | Nov 14, 2004 | Issued |
Array
(
[id] => 7375561
[patent_doc_number] => 20040219700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Method of manufacturing a light emitting semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/853175
[patent_app_country] => US
[patent_app_date] => 2004-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 5321
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[patent_words_short_claim] => 155
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20040219700.pdf
[firstpage_image] =>[orig_patent_app_number] => 10853175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/853175 | Method of manufacturing a light emitting semiconductor package | May 25, 2004 | Issued |
Array
(
[id] => 7620081
[patent_doc_number] => 06943102
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-13
[patent_title] => 'Solder bump transfer sheet, method for producing the same, and methods for fabricating semiconductor device and printed board'
[patent_app_type] => utility
[patent_app_number] => 10/747076
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6289
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[patent_words_short_claim] => 288
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/943/06943102.pdf
[firstpage_image] =>[orig_patent_app_number] => 10747076
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/747076 | Solder bump transfer sheet, method for producing the same, and methods for fabricating semiconductor device and printed board | Dec 29, 2003 | Issued |
Array
(
[id] => 7264074
[patent_doc_number] => 20040241951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Method of fabrication of thin film resistor with 0 TCR'
[patent_app_type] => new
[patent_app_number] => 10/727946
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4535
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20040241951.pdf
[firstpage_image] =>[orig_patent_app_number] => 10727946
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/727946 | Method of fabrication of thin film resistor with zero TCR | Dec 3, 2003 | Issued |
Array
(
[id] => 7301306
[patent_doc_number] => 20040113283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Method for fabricating encapsulated semiconductor components by etching'
[patent_app_type] => new
[patent_app_number] => 10/719876
[patent_app_country] => US
[patent_app_date] => 2003-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 22025
[patent_no_of_claims] => 260
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20040113283.pdf
[firstpage_image] =>[orig_patent_app_number] => 10719876
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/719876 | Method of fabricating encapsulated semiconductor components by etching | Nov 20, 2003 | Issued |
Array
(
[id] => 1014607
[patent_doc_number] => 06893949
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'Semiconductor devices having contact plugs and local interconnects and methods for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/696165
[patent_app_country] => US
[patent_app_date] => 2003-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/893/06893949.pdf
[firstpage_image] =>[orig_patent_app_number] => 10696165
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/696165 | Semiconductor devices having contact plugs and local interconnects and methods for making the same | Oct 27, 2003 | Issued |
Array
(
[id] => 7318941
[patent_doc_number] => 20040135260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Semiconductor devices and methods of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/694035
[patent_app_country] => US
[patent_app_date] => 2003-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1949
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20040135260.pdf
[firstpage_image] =>[orig_patent_app_number] => 10694035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/694035 | Methods to reduce stress on a metal interconnect | Oct 26, 2003 | Issued |
Array
(
[id] => 7154285
[patent_doc_number] => 20050082551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Large bumps for optical flip chips'
[patent_app_type] => utility
[patent_app_number] => 10/691136
[patent_app_country] => US
[patent_app_date] => 2003-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2670
[patent_no_of_claims] => 27
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20050082551.pdf
[firstpage_image] =>[orig_patent_app_number] => 10691136
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/691136 | Large bumps for optical flip chips | Oct 20, 2003 | Issued |
Array
(
[id] => 972104
[patent_doc_number] => 06936489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Method and system for electrically coupling a chip to chip package'
[patent_app_type] => utility
[patent_app_number] => 10/651594
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3104
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/936/06936489.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651594
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651594 | Method and system for electrically coupling a chip to chip package | Aug 28, 2003 | Issued |
Array
(
[id] => 975409
[patent_doc_number] => 06933176
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-08-23
[patent_title] => 'Ball grid array package and process for manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 10/647696
[patent_app_country] => US
[patent_app_date] => 2003-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 50
[patent_no_of_words] => 4074
[patent_no_of_claims] => 23
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/933/06933176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10647696
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/647696 | Ball grid array package and process for manufacturing same | Aug 24, 2003 | Issued |
Array
(
[id] => 975994
[patent_doc_number] => 06933611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-23
[patent_title] => 'Selective solder bump application'
[patent_app_type] => utility
[patent_app_number] => 10/629055
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2996
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/933/06933611.pdf
[firstpage_image] =>[orig_patent_app_number] => 10629055
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/629055 | Selective solder bump application | Jul 28, 2003 | Issued |
Array
(
[id] => 1059535
[patent_doc_number] => 06852625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/617726
[patent_app_country] => US
[patent_app_date] => 2003-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/852/06852625.pdf
[firstpage_image] =>[orig_patent_app_number] => 10617726
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617726 | Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same | Jul 13, 2003 | Issued |
Array
(
[id] => 1040983
[patent_doc_number] => 06870252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-22
[patent_title] => 'Chip packaging and connection for reduced EMI'
[patent_app_type] => utility
[patent_app_number] => 10/464646
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/870/06870252.pdf
[firstpage_image] =>[orig_patent_app_number] => 10464646
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/464646 | Chip packaging and connection for reduced EMI | Jun 17, 2003 | Issued |
Array
(
[id] => 996511
[patent_doc_number] => 06913950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Semiconductor device with chamfered substrate and method of making the same'
[patent_app_type] => utility
[patent_app_number] => 10/457637
[patent_app_country] => US
[patent_app_date] => 2003-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/913/06913950.pdf
[firstpage_image] =>[orig_patent_app_number] => 10457637
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/457637 | Semiconductor device with chamfered substrate and method of making the same | Jun 8, 2003 | Issued |
Array
(
[id] => 6662207
[patent_doc_number] => 20030201533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Laminated chip component and manufacturing method'
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[patent_app_number] => 10/434076
[patent_app_country] => US
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[pdf_file] => publications/A1/0201/20030201533.pdf
[firstpage_image] =>[orig_patent_app_number] => 10434076
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/434076 | Laminated chip component and manufacturing method | May 8, 2003 | Abandoned |
Array
(
[id] => 6662196
[patent_doc_number] => 20030201522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Semiconductor device having improved alignment of an electrode terminal on a semiconductor chip and a conductor coupled to the electrode terminal'
[patent_app_type] => new
[patent_app_number] => 10/410175
[patent_app_country] => US
[patent_app_date] => 2003-04-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0201/20030201522.pdf
[firstpage_image] =>[orig_patent_app_number] => 10410175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/410175 | Semiconductor device having improved alignment of an electrode terminal on a semiconductor chip and a conductor coupled to the electrode terminal | Apr 9, 2003 | Issued |
Array
(
[id] => 7617132
[patent_doc_number] => 06946308
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-20
[patent_title] => 'Method of manufacturing III-V group compound semiconductor'
[patent_app_type] => utility
[patent_app_number] => 10/396565
[patent_app_country] => US
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[pdf_file] => patents/06/946/06946308.pdf
[firstpage_image] =>[orig_patent_app_number] => 10396565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396565 | Method of manufacturing III-V group compound semiconductor | Mar 25, 2003 | Issued |
Array
(
[id] => 6845375
[patent_doc_number] => 20030164542
[patent_country] => US
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[patent_issue_date] => 2003-09-04
[patent_title] => 'Stacked semiconductor device including improved lead frame arrangement'
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[firstpage_image] =>[orig_patent_app_number] => 10377713
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/377713 | Stacked semiconductor device including improved lead frame arrangement | Mar 3, 2003 | Issued |
Array
(
[id] => 1138399
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[patent_title] => 'Etch back of interconnect dielectrics'
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[patent_app_number] => 10/375996
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10375996
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/375996 | Etch back of interconnect dielectrics | Feb 27, 2003 | Issued |
Array
(
[id] => 1065628
[patent_doc_number] => 06846754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-25
[patent_title] => 'Boron phosphide-based semiconductor layer and vapor phase growth method thereof'
[patent_app_type] => utility
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[pdf_file] => patents/06/846/06846754.pdf
[firstpage_image] =>[orig_patent_app_number] => 10369556
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/369556 | Boron phosphide-based semiconductor layer and vapor phase growth method thereof | Feb 20, 2003 | Issued |