Search

Nema O. Berezny

Examiner (ID: 9201)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
286
Issued Applications
250
Pending Applications
5
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4312095 [patent_doc_number] => 06242286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Multilayer high density micro circuit module and method of manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/275055 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2879 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242286.pdf [firstpage_image] =>[orig_patent_app_number] => 275055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275055
Multilayer high density micro circuit module and method of manufacturing same Mar 22, 1999 Issued
Array ( [id] => 1507430 [patent_doc_number] => 06440836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method for forming solder bumps on flip chips and devices formed' [patent_app_type] => B1 [patent_app_number] => 09/268785 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 5374 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440836.pdf [firstpage_image] =>[orig_patent_app_number] => 09268785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268785
Method for forming solder bumps on flip chips and devices formed Mar 15, 1999 Issued
Array ( [id] => 4190778 [patent_doc_number] => 06043108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Lead frame with lead-securing tape bonded to the inner lead sections of plural leads and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/270185 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3132 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043108.pdf [firstpage_image] =>[orig_patent_app_number] => 270185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270185
Lead frame with lead-securing tape bonded to the inner lead sections of plural leads and a method of manufacturing the same Mar 14, 1999 Issued
Array ( [id] => 4188766 [patent_doc_number] => 06153506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Integrated circuit having reduced probability of wire-bond failure' [patent_app_type] => 1 [patent_app_number] => 9/263075 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2398 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153506.pdf [firstpage_image] =>[orig_patent_app_number] => 263075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263075
Integrated circuit having reduced probability of wire-bond failure Mar 7, 1999 Issued
Array ( [id] => 4357259 [patent_doc_number] => 06174788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Partial semiconductor wafer processing with multiple cuts of random sizes' [patent_app_type] => 1 [patent_app_number] => 9/262265 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3098 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174788.pdf [firstpage_image] =>[orig_patent_app_number] => 262265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262265
Partial semiconductor wafer processing with multiple cuts of random sizes Mar 3, 1999 Issued
Array ( [id] => 4155978 [patent_doc_number] => 06156625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Partial semiconductor wafer processing using wafermap display' [patent_app_type] => 1 [patent_app_number] => 9/262554 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 2594 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156625.pdf [firstpage_image] =>[orig_patent_app_number] => 262554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262554
Partial semiconductor wafer processing using wafermap display Mar 3, 1999 Issued
Array ( [id] => 1297255 [patent_doc_number] => 06627483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method for mounting an electronic component' [patent_app_type] => B2 [patent_app_number] => 09/260795 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 7839 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627483.pdf [firstpage_image] =>[orig_patent_app_number] => 09260795 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260795
Method for mounting an electronic component Feb 28, 1999 Issued
Array ( [id] => 4155990 [patent_doc_number] => 06156626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Electromigration bonding process and system' [patent_app_type] => 1 [patent_app_number] => 9/259744 [patent_app_country] => US [patent_app_date] => 1999-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156626.pdf [firstpage_image] =>[orig_patent_app_number] => 259744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259744
Electromigration bonding process and system Feb 26, 1999 Issued
Array ( [id] => 6898580 [patent_doc_number] => 20010046745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'BITLINE DIFFUSION WITH HALO FOR IMPROVED ARRAY THRESHOLD VOLTAGE CONTROL' [patent_app_type] => new [patent_app_number] => 09/257817 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3596 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046745.pdf [firstpage_image] =>[orig_patent_app_number] => 09257817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257817
Bitline diffusion with halo for improved array threshold voltage control Feb 24, 1999 Issued
Array ( [id] => 1545362 [patent_doc_number] => 06444563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and apparatus for extending fatigue life of solder joints in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/253876 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444563.pdf [firstpage_image] =>[orig_patent_app_number] => 09253876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253876
Method and apparatus for extending fatigue life of solder joints in a semiconductor device Feb 21, 1999 Issued
Array ( [id] => 4357274 [patent_doc_number] => 06174789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of dividing a compound semiconductor wafer into pellets by utilizing extremely narrow scribe regions' [patent_app_type] => 1 [patent_app_number] => 9/250164 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6329 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174789.pdf [firstpage_image] =>[orig_patent_app_number] => 250164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250164
Method of dividing a compound semiconductor wafer into pellets by utilizing extremely narrow scribe regions Feb 15, 1999 Issued
Array ( [id] => 4155647 [patent_doc_number] => 06114240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for fabricating semiconductor components using focused laser beam' [patent_app_type] => 1 [patent_app_number] => 9/250289 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 6813 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114240.pdf [firstpage_image] =>[orig_patent_app_number] => 250289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250289
Method for fabricating semiconductor components using focused laser beam Feb 11, 1999 Issued
Array ( [id] => 4141417 [patent_doc_number] => 06030855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Self-aligned connector for stacked chip module' [patent_app_type] => 1 [patent_app_number] => 9/246435 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3236 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030855.pdf [firstpage_image] =>[orig_patent_app_number] => 246435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246435
Self-aligned connector for stacked chip module Feb 7, 1999 Issued
Array ( [id] => 4172175 [patent_doc_number] => 06083775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method of encapsulating a chip' [patent_app_type] => 1 [patent_app_number] => 9/245439 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3401 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083775.pdf [firstpage_image] =>[orig_patent_app_number] => 245439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245439
Method of encapsulating a chip Feb 4, 1999 Issued
Array ( [id] => 4257834 [patent_doc_number] => 06204094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method and apparatus for populating an adhesive sheet with particles' [patent_app_type] => 1 [patent_app_number] => 9/241714 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204094.pdf [firstpage_image] =>[orig_patent_app_number] => 241714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241714
Method and apparatus for populating an adhesive sheet with particles Feb 1, 1999 Issued
Array ( [id] => 4172162 [patent_doc_number] => 06083774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method of fabricating a flip chip mold injected package' [patent_app_type] => 1 [patent_app_number] => 9/240575 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083774.pdf [firstpage_image] =>[orig_patent_app_number] => 240575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/240575
Method of fabricating a flip chip mold injected package Jan 31, 1999 Issued
Array ( [id] => 4233541 [patent_doc_number] => 06074897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Integrated circuit bonding method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/238706 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4870 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074897.pdf [firstpage_image] =>[orig_patent_app_number] => 238706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238706
Integrated circuit bonding method and apparatus Jan 27, 1999 Issued
Array ( [id] => 4328698 [patent_doc_number] => 06312975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor package and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/237345 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312975.pdf [firstpage_image] =>[orig_patent_app_number] => 237345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237345
Semiconductor package and method of manufacturing the same Jan 25, 1999 Issued
Array ( [id] => 4294294 [patent_doc_number] => 06184109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method of dividing a wafer and method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/234505 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 50 [patent_no_of_words] => 9717 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184109.pdf [firstpage_image] =>[orig_patent_app_number] => 234505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234505
Method of dividing a wafer and method of manufacturing a semiconductor device Jan 20, 1999 Issued
Array ( [id] => 4094161 [patent_doc_number] => 06096577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of making semiconductor device, and film carrier tape' [patent_app_type] => 1 [patent_app_number] => 9/180896 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4001 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096577.pdf [firstpage_image] =>[orig_patent_app_number] => 180896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/180896
Method of making semiconductor device, and film carrier tape Jan 14, 1999 Issued
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