Search

Nema O. Berezny

Examiner (ID: 12635)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
286
Issued Applications
250
Pending Applications
5
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4312078 [patent_doc_number] => 06242285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Stacked package of semiconductor package units via direct connection between leads and stacking method therefor' [patent_app_type] => 1 [patent_app_number] => 9/232026 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 5923 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242285.pdf [firstpage_image] =>[orig_patent_app_number] => 232026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232026
Stacked package of semiconductor package units via direct connection between leads and stacking method therefor Jan 14, 1999 Issued
Array ( [id] => 4409196 [patent_doc_number] => 06228762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Methods for forming contact holes having sidewalls with smooth profiles' [patent_app_type] => 1 [patent_app_number] => 9/231339 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2371 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228762.pdf [firstpage_image] =>[orig_patent_app_number] => 231339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231339
Methods for forming contact holes having sidewalls with smooth profiles Jan 12, 1999 Issued
Array ( [id] => 4099600 [patent_doc_number] => 06066512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Semiconductor device, method of fabricating the same, and electronic apparatus' [patent_app_type] => 1 [patent_app_number] => 9/227895 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5403 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066512.pdf [firstpage_image] =>[orig_patent_app_number] => 227895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227895
Semiconductor device, method of fabricating the same, and electronic apparatus Jan 10, 1999 Issued
Array ( [id] => 4235202 [patent_doc_number] => 06143590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Multi-chip semiconductor device and method of producing the same' [patent_app_type] => 1 [patent_app_number] => 9/227965 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 12234 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143590.pdf [firstpage_image] =>[orig_patent_app_number] => 227965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227965
Multi-chip semiconductor device and method of producing the same Jan 10, 1999 Issued
Array ( [id] => 4100075 [patent_doc_number] => 06066546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method to minimize particulate induced clamping failures' [patent_app_type] => 1 [patent_app_number] => 9/227644 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1837 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066546.pdf [firstpage_image] =>[orig_patent_app_number] => 227644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227644
Method to minimize particulate induced clamping failures Jan 7, 1999 Issued
Array ( [id] => 4357874 [patent_doc_number] => 06255145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product' [patent_app_type] => 1 [patent_app_number] => 9/227696 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255145.pdf [firstpage_image] =>[orig_patent_app_number] => 227696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227696
Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product Jan 7, 1999 Issued
Array ( [id] => 4404338 [patent_doc_number] => 06271058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board' [patent_app_type] => 1 [patent_app_number] => 9/225446 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5807 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271058.pdf [firstpage_image] =>[orig_patent_app_number] => 225446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225446
Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board Jan 5, 1999 Issued
Array ( [id] => 4214153 [patent_doc_number] => 06110762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method of manufacturing a custom corner attach heat sink design for a plastic ball grid array integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 9/225416 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1115 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110762.pdf [firstpage_image] =>[orig_patent_app_number] => 225416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225416
Method of manufacturing a custom corner attach heat sink design for a plastic ball grid array integrated circuit package Jan 4, 1999 Issued
Array ( [id] => 4348915 [patent_doc_number] => 06214750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Alternative structure to SOI using proton beams' [patent_app_type] => 1 [patent_app_number] => 9/225376 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214750.pdf [firstpage_image] =>[orig_patent_app_number] => 225376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225376
Alternative structure to SOI using proton beams Jan 3, 1999 Issued
Array ( [id] => 4369326 [patent_doc_number] => 06287961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Dual damascene patterned conductor layer formation method without etch stop layer' [patent_app_type] => 1 [patent_app_number] => 9/225380 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9435 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287961.pdf [firstpage_image] =>[orig_patent_app_number] => 225380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225380
Dual damascene patterned conductor layer formation method without etch stop layer Jan 3, 1999 Issued
Array ( [id] => 4327326 [patent_doc_number] => 06319818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Pattern factor checkerboard for planarization' [patent_app_type] => 1 [patent_app_number] => 9/224778 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319818.pdf [firstpage_image] =>[orig_patent_app_number] => 224778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224778
Pattern factor checkerboard for planarization Jan 3, 1999 Issued
Array ( [id] => 4287102 [patent_doc_number] => 06211097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Planarization process' [patent_app_type] => 1 [patent_app_number] => 9/223398 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1759 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211097.pdf [firstpage_image] =>[orig_patent_app_number] => 223398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223398
Planarization process Dec 29, 1998 Issued
Array ( [id] => 3942040 [patent_doc_number] => 05989994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for producing contact structures' [patent_app_type] => 1 [patent_app_number] => 9/222176 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 3639 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989994.pdf [firstpage_image] =>[orig_patent_app_number] => 222176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222176
Method for producing contact structures Dec 28, 1998 Issued
Array ( [id] => 4107111 [patent_doc_number] => 06057174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor device, method of fabricating the same, and electronic apparatus' [patent_app_type] => 1 [patent_app_number] => 9/220595 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3417 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057174.pdf [firstpage_image] =>[orig_patent_app_number] => 220595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/220595
Semiconductor device, method of fabricating the same, and electronic apparatus Dec 27, 1998 Issued
Array ( [id] => 4287073 [patent_doc_number] => 06211095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for relieving lattice mismatch stress in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/221025 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1536 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211095.pdf [firstpage_image] =>[orig_patent_app_number] => 221025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221025
Method for relieving lattice mismatch stress in semiconductor devices Dec 22, 1998 Issued
Array ( [id] => 4153869 [patent_doc_number] => 06103554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method for packaging integrated circuits with elastomer chip carriers' [patent_app_type] => 1 [patent_app_number] => 9/219015 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2829 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103554.pdf [firstpage_image] =>[orig_patent_app_number] => 219015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/219015
Method for packaging integrated circuits with elastomer chip carriers Dec 22, 1998 Issued
Array ( [id] => 4350152 [patent_doc_number] => 06291285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for protecting gate oxide layer and monitoring damage' [patent_app_type] => 1 [patent_app_number] => 9/215884 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1852 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291285.pdf [firstpage_image] =>[orig_patent_app_number] => 215884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215884
Method for protecting gate oxide layer and monitoring damage Dec 15, 1998 Issued
Array ( [id] => 4138899 [patent_doc_number] => 06060336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore' [patent_app_type] => 1 [patent_app_number] => 9/211486 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2441 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060336.pdf [firstpage_image] =>[orig_patent_app_number] => 211486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211486
Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore Dec 10, 1998 Issued
Array ( [id] => 4100233 [patent_doc_number] => 06066557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method for fabricating protected copper metallization' [patent_app_type] => 1 [patent_app_number] => 9/208246 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066557.pdf [firstpage_image] =>[orig_patent_app_number] => 208246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208246
Method for fabricating protected copper metallization Dec 8, 1998 Issued
Array ( [id] => 4070992 [patent_doc_number] => 06069066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method of forming bonding pad' [patent_app_type] => 1 [patent_app_number] => 9/208025 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1570 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069066.pdf [firstpage_image] =>[orig_patent_app_number] => 208025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208025
Method of forming bonding pad Dec 8, 1998 Issued
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