Nema O. Berezny

Array ( [id] => 4419792 [patent_doc_number] => 06177348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Low temperature via fill using liquid phase transport' [patent_app_type] => 1 [patent_app_number] => 9/009446 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2412 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177348.pdf [firstpage_image] =>[orig_patent_app_number] => 009446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081085 [patent_doc_number] => 06054373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method of and apparatus for removing metallic impurities diffused in a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/006996 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4650 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054373.pdf [firstpage_image] =>[orig_patent_app_number] => 006996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4085980 [patent_doc_number] => 06017823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method of forming a MOS field effect transistor with improved gate side wall insulation films' [patent_app_type] => 1 [patent_app_number] => 8/998626 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 5832 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017823.pdf [firstpage_image] =>[orig_patent_app_number] => 998626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4004759 [patent_doc_number] => 05960322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Suppression of boron segregation for shallow source and drain junctions in semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/994308 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2155 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960322.pdf [firstpage_image] =>[orig_patent_app_number] => 994308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152575 [patent_doc_number] => 06107109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate' [patent_app_type] => 1 [patent_app_number] => 8/993965 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 33 [patent_no_of_words] => 9177 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107109.pdf [firstpage_image] =>[orig_patent_app_number] => 993965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4107647 [patent_doc_number] => 06057211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method for manufacturing an integrated circuit arrangement' [patent_app_type] => 1 [patent_app_number] => 8/990516 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4140 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057211.pdf [firstpage_image] =>[orig_patent_app_number] => 990516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6276874 [patent_doc_number] => 20020106832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'METHOD AND APPARATUS FOR ATTACHING SOLDER MEMBERS TO A SUBSTRATE' [patent_app_type] => new [patent_app_number] => 08/964734 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7061 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106832.pdf [firstpage_image] =>[orig_patent_app_number] => 08964734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099626 [patent_doc_number] => 06066514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Adhesion enhanced semiconductor die for mold compound packaging' [patent_app_type] => 1 [patent_app_number] => 8/963395 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1737 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066514.pdf [firstpage_image] =>[orig_patent_app_number] => 963395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206842 [patent_doc_number] => 06027987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method of manufacturing a crystalline semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/962234 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 22 [patent_no_of_words] => 3709 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027987.pdf [firstpage_image] =>[orig_patent_app_number] => 962234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131814 [patent_doc_number] => 06146999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method for forming metal line of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/956387 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2249 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146999.pdf [firstpage_image] =>[orig_patent_app_number] => 956387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3935655 [patent_doc_number] => 05972802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Prevention of edge stain in silicon wafers by ozone dipping' [patent_app_type] => 1 [patent_app_number] => 8/944542 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1047 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972802.pdf [firstpage_image] =>[orig_patent_app_number] => 944542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155589 [patent_doc_number] => 06114236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Process for production of semiconductor device having an insulating film of low dielectric constant' [patent_app_type] => 1 [patent_app_number] => 8/946224 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3146 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114236.pdf [firstpage_image] =>[orig_patent_app_number] => 946224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236326 [patent_doc_number] => 06143668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'KLXX technology with integrated passivation process, probe geometry and probing process' [patent_app_type] => 1 [patent_app_number] => 8/941795 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7722 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143668.pdf [firstpage_image] =>[orig_patent_app_number] => 941795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4064315 [patent_doc_number] => 06008119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Chemical-mechanical polishing of semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/940762 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3969 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008119.pdf [firstpage_image] =>[orig_patent_app_number] => 940762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4203506 [patent_doc_number] => 06013937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Buffer layer for improving control of layer thickness' [patent_app_type] => 1 [patent_app_number] => 8/938196 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3631 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013937.pdf [firstpage_image] =>[orig_patent_app_number] => 938196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994622 [patent_doc_number] => 05918152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Gap filling method using high pressure' [patent_app_type] => 1 [patent_app_number] => 8/933368 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918152.pdf [firstpage_image] =>[orig_patent_app_number] => 933368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4168770 [patent_doc_number] => 06140163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method and apparatus for upper level substrate isolation integrated with bulk silicon' [patent_app_type] => 1 [patent_app_number] => 8/893744 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140163.pdf [firstpage_image] =>[orig_patent_app_number] => 893744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4234122 [patent_doc_number] => 06074935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of reducing the formation of watermarks on semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/882057 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1808 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074935.pdf [firstpage_image] =>[orig_patent_app_number] => 882057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081422 [patent_doc_number] => 06054396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Semiconductor processing method of reducing thickness depletion of a silicide layer at a junction of different underlying layers' [patent_app_type] => 1 [patent_app_number] => 8/868042 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1898 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054396.pdf [firstpage_image] =>[orig_patent_app_number] => 868042 [rel_patent_id] =>[rel_patent_doc_number] =>)