Search

Nema O. Berezny

Examiner (ID: 9201)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
286
Issued Applications
250
Pending Applications
5
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6669014 [patent_doc_number] => 20030113998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Flex tab for use in stacking packaged integrated circuit chips' [patent_app_type] => new [patent_app_number] => 10/024389 [patent_app_country] => US [patent_app_date] => 2001-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113998.pdf [firstpage_image] =>[orig_patent_app_number] => 10024389 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024389
Flex tab for use in stacking packaged integrated circuit chips Dec 16, 2001 Abandoned
Array ( [id] => 1354177 [patent_doc_number] => 06576497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Chip-type electronic component' [patent_app_type] => B2 [patent_app_number] => 10/014856 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 47 [patent_no_of_words] => 12505 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576497.pdf [firstpage_image] =>[orig_patent_app_number] => 10014856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014856
Chip-type electronic component Dec 13, 2001 Issued
Array ( [id] => 6237544 [patent_doc_number] => 20020043705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => new [patent_app_number] => 10/006479 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2602 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043705.pdf [firstpage_image] =>[orig_patent_app_number] => 10006479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/006479
Semiconductor device and its manufacturing method Dec 5, 2001 Abandoned
Array ( [id] => 6092066 [patent_doc_number] => 20020050632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Magnetic shielding for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/003116 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2878 [patent_no_of_claims] => 96 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20020050632.pdf [firstpage_image] =>[orig_patent_app_number] => 10003116 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003116
Method of forming a structure for supporting an integrated circuit chip Dec 5, 2001 Issued
Array ( [id] => 6694901 [patent_doc_number] => 20030107095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Single chip multiple range pressure transducer device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/010975 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107095.pdf [firstpage_image] =>[orig_patent_app_number] => 10010975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010975
Single chip multiple range pressure transducer device Dec 5, 2001 Issued
10/011158 Flip chip mounted to thermal sensing element through the back side of the chip Dec 4, 2001 Abandoned
Array ( [id] => 1326900 [patent_doc_number] => 06599777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method for mounting flip chip on circuit board through reliable electrical connections at low contact resistance' [patent_app_type] => B2 [patent_app_number] => 09/997686 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4784 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599777.pdf [firstpage_image] =>[orig_patent_app_number] => 09997686 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997686
Method for mounting flip chip on circuit board through reliable electrical connections at low contact resistance Nov 28, 2001 Issued
Array ( [id] => 1218082 [patent_doc_number] => 06707135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Semiconductor leadframe for staggered board attach' [patent_app_type] => B2 [patent_app_number] => 09/990846 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4066 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707135.pdf [firstpage_image] =>[orig_patent_app_number] => 09990846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990846
Semiconductor leadframe for staggered board attach Nov 20, 2001 Issued
Array ( [id] => 1232493 [patent_doc_number] => 06693362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Multichip module having chips mounted on upper and under surfaces of a thin film closing an opening formed in a rigid substrate' [patent_app_type] => B2 [patent_app_number] => 09/988575 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 6052 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693362.pdf [firstpage_image] =>[orig_patent_app_number] => 09988575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988575
Multichip module having chips mounted on upper and under surfaces of a thin film closing an opening formed in a rigid substrate Nov 19, 2001 Issued
Array ( [id] => 6081006 [patent_doc_number] => 20020081768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Semiconductor device and method of fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 09/992315 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4752 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081768.pdf [firstpage_image] =>[orig_patent_app_number] => 09992315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992315
Semiconductor device and method of fabricating semiconductor device Nov 18, 2001 Abandoned
Array ( [id] => 6801283 [patent_doc_number] => 20030096448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Selective solder bump application' [patent_app_type] => new [patent_app_number] => 10/016039 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2992 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096448.pdf [firstpage_image] =>[orig_patent_app_number] => 10016039 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016039
Selective solder bump application Nov 15, 2001 Issued
Array ( [id] => 6651121 [patent_doc_number] => 20030008432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method and device for securing a multi-dimensionally constructed chip stack and chip configuration' [patent_app_type] => new [patent_app_number] => 10/002925 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008432.pdf [firstpage_image] =>[orig_patent_app_number] => 10002925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002925
Method and device for securing a multi-dimensionally constructed chip stack and chip configuration Nov 1, 2001 Issued
Array ( [id] => 1297500 [patent_doc_number] => 06627531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Three dimensional device integration method and integrated device' [patent_app_type] => B2 [patent_app_number] => 09/983808 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 57 [patent_no_of_words] => 11989 [patent_no_of_claims] => 118 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627531.pdf [firstpage_image] =>[orig_patent_app_number] => 09983808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983808
Three dimensional device integration method and integrated device Oct 24, 2001 Issued
Array ( [id] => 6536342 [patent_doc_number] => 20020163077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Semiconductor device with layered semiconductor chips' [patent_app_type] => new [patent_app_number] => 09/983390 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4383 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163077.pdf [firstpage_image] =>[orig_patent_app_number] => 09983390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983390
Semiconductor device with layered semiconductor chips Oct 23, 2001 Issued
Array ( [id] => 1174977 [patent_doc_number] => 06746897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Fabrication process of semiconductor package and semiconductor package' [patent_app_type] => B2 [patent_app_number] => 10/008616 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 135 [patent_no_of_words] => 15582 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746897.pdf [firstpage_image] =>[orig_patent_app_number] => 10008616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/008616
Fabrication process of semiconductor package and semiconductor package Oct 22, 2001 Issued
Array ( [id] => 6277191 [patent_doc_number] => 20020106883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Solder bump transfer sheet, method for producing the same, and methods for fabricating semiconductor device and printed board' [patent_app_type] => new [patent_app_number] => 09/978176 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6359 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106883.pdf [firstpage_image] =>[orig_patent_app_number] => 09978176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978176
Solder bump transfer sheet, method for producing the same, and methods for fabricating semiconductor device and printed board Oct 16, 2001 Issued
Array ( [id] => 6811784 [patent_doc_number] => 20030071334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method and system for electrically coupling a chip to chip package' [patent_app_type] => new [patent_app_number] => 09/978983 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3099 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20030071334.pdf [firstpage_image] =>[orig_patent_app_number] => 09978983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978983
Method and system for electrically coupling a chip to chip package Oct 14, 2001 Issued
Array ( [id] => 1441048 [patent_doc_number] => 06495908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Multi-chip semiconductor package' [patent_app_type] => B2 [patent_app_number] => 09/973359 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3497 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495908.pdf [firstpage_image] =>[orig_patent_app_number] => 09973359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973359
Multi-chip semiconductor package Oct 8, 2001 Issued
Array ( [id] => 6817881 [patent_doc_number] => 20030068839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Forming solder walls and interconnects on a substrate' [patent_app_type] => new [patent_app_number] => 09/972695 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1201 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068839.pdf [firstpage_image] =>[orig_patent_app_number] => 09972695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972695
Forming solder walls and interconnects on a substrate Oct 3, 2001 Abandoned
Array ( [id] => 6783098 [patent_doc_number] => 20030064545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Low profile stacked multi-chip package and method of forming same' [patent_app_type] => new [patent_app_number] => 09/968365 [patent_app_country] => US [patent_app_date] => 2001-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2720 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20030064545.pdf [firstpage_image] =>[orig_patent_app_number] => 09968365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968365
Low profile stacked multi-chip package and method of forming same Sep 29, 2001 Issued
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