
Nema O. Berezny
Examiner (ID: 9201)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 286 |
| Issued Applications | 250 |
| Pending Applications | 5 |
| Abandoned Applications | 31 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4326217
[patent_doc_number] => 06319746
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Optical semiconductor device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/691886
[patent_app_country] => US
[patent_app_date] => 2000-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 11
[patent_no_of_words] => 2561
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319746.pdf
[firstpage_image] =>[orig_patent_app_number] => 691886
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/691886 | Optical semiconductor device and method for fabricating the same | Oct 19, 2000 | Issued |
Array
(
[id] => 1280828
[patent_doc_number] => 06642080
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Chip-on-chip interconnections of varied characterstics'
[patent_app_type] => B1
[patent_app_number] => 09/691546
[patent_app_country] => US
[patent_app_date] => 2000-10-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/642/06642080.pdf
[firstpage_image] =>[orig_patent_app_number] => 09691546
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/691546 | Chip-on-chip interconnections of varied characterstics | Oct 17, 2000 | Issued |
Array
(
[id] => 1229988
[patent_doc_number] => 06696747
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'Semiconductor package having reduced thickness'
[patent_app_type] => B1
[patent_app_number] => 09/687585
[patent_app_country] => US
[patent_app_date] => 2000-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1991
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[pdf_file] => patents/06/696/06696747.pdf
[firstpage_image] =>[orig_patent_app_number] => 09687585
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/687585 | Semiconductor package having reduced thickness | Oct 12, 2000 | Issued |
Array
(
[id] => 1281428
[patent_doc_number] => 06646339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-11
[patent_title] => 'Thin and heat radiant semiconductor package and method for manufacturing'
[patent_app_type] => B1
[patent_app_number] => 09/687787
[patent_app_country] => US
[patent_app_date] => 2000-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3415
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[pdf_file] => patents/06/646/06646339.pdf
[firstpage_image] =>[orig_patent_app_number] => 09687787
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/687787 | Thin and heat radiant semiconductor package and method for manufacturing | Oct 12, 2000 | Issued |
Array
(
[id] => 1288704
[patent_doc_number] => 06639308
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Near chip size semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/687876
[patent_app_country] => US
[patent_app_date] => 2000-10-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/639/06639308.pdf
[firstpage_image] =>[orig_patent_app_number] => 09687876
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/687876 | Near chip size semiconductor package | Oct 12, 2000 | Issued |
Array
(
[id] => 1379471
[patent_doc_number] => 06555469
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Chip scale packages'
[patent_app_type] => B1
[patent_app_number] => 09/686016
[patent_app_country] => US
[patent_app_date] => 2000-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/555/06555469.pdf
[firstpage_image] =>[orig_patent_app_number] => 09686016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/686016 | Chip scale packages | Oct 9, 2000 | Issued |
Array
(
[id] => 1165105
[patent_doc_number] => 06756253
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Method for fabricating a semiconductor component with external contact polymer support layer'
[patent_app_type] => B1
[patent_app_number] => 09/653366
[patent_app_country] => US
[patent_app_date] => 2000-09-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756253.pdf
[firstpage_image] =>[orig_patent_app_number] => 09653366
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653366 | Method for fabricating a semiconductor component with external contact polymer support layer | Aug 31, 2000 | Issued |
Array
(
[id] => 1424505
[patent_doc_number] => 06515358
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Integrated passivation process, probe geometry and probing process'
[patent_app_type] => B1
[patent_app_number] => 09/651388
[patent_app_country] => US
[patent_app_date] => 2000-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 7605
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[pdf_file] => patents/06/515/06515358.pdf
[firstpage_image] =>[orig_patent_app_number] => 09651388
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/651388 | Integrated passivation process, probe geometry and probing process | Aug 28, 2000 | Issued |
Array
(
[id] => 1362030
[patent_doc_number] => 06569764
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material'
[patent_app_type] => B1
[patent_app_number] => 09/650076
[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 28
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[pdf_file] => patents/06/569/06569764.pdf
[firstpage_image] =>[orig_patent_app_number] => 09650076
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/650076 | Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material | Aug 28, 2000 | Issued |
Array
(
[id] => 1490077
[patent_doc_number] => 06417027
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'High density stackable and flexible substrate-based devices and systems and methods of fabricating'
[patent_app_type] => B1
[patent_app_number] => 09/645256
[patent_app_country] => US
[patent_app_date] => 2000-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/417/06417027.pdf
[firstpage_image] =>[orig_patent_app_number] => 09645256
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/645256 | High density stackable and flexible substrate-based devices and systems and methods of fabricating | Aug 23, 2000 | Issued |
Array
(
[id] => 1545054
[patent_doc_number] => 06444496
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Thermal paste preforms as a heat transfer media between a chip and a heat sink and method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/619886
[patent_app_country] => US
[patent_app_date] => 2000-07-20
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[pdf_file] => patents/06/444/06444496.pdf
[firstpage_image] =>[orig_patent_app_number] => 09619886
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/619886 | Thermal paste preforms as a heat transfer media between a chip and a heat sink and method thereof | Jul 19, 2000 | Issued |
Array
(
[id] => 1600203
[patent_doc_number] => 06475830
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Flip chip and packaged memory module'
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[patent_app_number] => 09/618975
[patent_app_country] => US
[patent_app_date] => 2000-07-19
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[firstpage_image] =>[orig_patent_app_number] => 09618975
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/618975 | Flip chip and packaged memory module | Jul 18, 2000 | Issued |
Array
(
[id] => 1497213
[patent_doc_number] => 06404064
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[patent_issue_date] => 2002-06-11
[patent_title] => 'Flip-chip bonding structure on substrate for flip-chip package application'
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[patent_app_date] => 2000-07-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/617717 | Flip-chip bonding structure on substrate for flip-chip package application | Jul 16, 2000 | Issued |
Array
(
[id] => 7612461
[patent_doc_number] => 06903375
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-07
[patent_title] => 'Solid-state image device, camera using the same, and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 09/613795
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[firstpage_image] =>[orig_patent_app_number] => 09613795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/613795 | Solid-state image device, camera using the same, and method of manufacturing the same | Jul 10, 2000 | Issued |
| 09/612576 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding | Jul 6, 2000 | Abandoned |
Array
(
[id] => 6618444
[patent_doc_number] => 20020064931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-30
[patent_title] => 'Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure'
[patent_app_type] => new
[patent_app_number] => 09/609626
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/609626 | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure | Jul 2, 2000 | Abandoned |
Array
(
[id] => 728297
[patent_doc_number] => 07041533
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-09
[patent_title] => 'Stereolithographic method for fabricating stabilizers for semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 09/590621
[patent_app_country] => US
[patent_app_date] => 2000-06-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09590621
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590621 | Stereolithographic method for fabricating stabilizers for semiconductor devices | Jun 7, 2000 | Issued |
Array
(
[id] => 4336019
[patent_doc_number] => 06333210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Process of ensuring detect free placement by solder coating on package pads'
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[patent_app_number] => 9/577675
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/577675 | Process of ensuring detect free placement by solder coating on package pads | May 24, 2000 | Issued |
Array
(
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[patent_title] => 'Semiconductor device and manufacturing method thereof, circuit board and electronic equipment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/555135 | Semiconductor device and manufacturing method thereof, circuit board and electronic equipment | May 24, 2000 | Issued |
Array
(
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[patent_title] => 'Thin-film structure having reliably removable oxide layer formed on bump exposed at surface of insulating layer and manufacturing method therefor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/569155 | Thin-film structure having reliably removable oxide layer formed on bump exposed at surface of insulating layer and manufacturing method therefor | May 10, 2000 | Issued |