Nema O. Berezny

Array ( [id] => 979038 [patent_doc_number] => 06930042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Method for producing a semiconductor component with at least one encapsulated chip on a substrate' [patent_app_type] => utility [patent_app_number] => 09/568945 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3028 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930042.pdf [firstpage_image] =>[orig_patent_app_number] => 09568945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1458689 [patent_doc_number] => 06426242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor chip packaging method' [patent_app_type] => B1 [patent_app_number] => 09/565936 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2969 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426242.pdf [firstpage_image] =>[orig_patent_app_number] => 09565936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4274930 [patent_doc_number] => 06281046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of forming an integrated circuit package at a wafer level' [patent_app_type] => 1 [patent_app_number] => 9/558396 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281046.pdf [firstpage_image] =>[orig_patent_app_number] => 558396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1594264 [patent_doc_number] => 06383843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Using removable spacers to ensure adequate bondline thickness' [patent_app_type] => B1 [patent_app_number] => 09/551625 [patent_app_country] => US [patent_app_date] => 2000-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1895 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383843.pdf [firstpage_image] =>[orig_patent_app_number] => 09551625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1231313 [patent_doc_number] => 06692993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Windowed non-ceramic package having embedded frame' [patent_app_type] => B2 [patent_app_number] => 09/546225 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3617 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/692/06692993.pdf [firstpage_image] =>[orig_patent_app_number] => 09546225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418869 [patent_doc_number] => 06506629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages' [patent_app_type] => B1 [patent_app_number] => 09/538685 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5181 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506629.pdf [firstpage_image] =>[orig_patent_app_number] => 09538685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1517187 [patent_doc_number] => 06500694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Three dimensional device integration method and integrated device' [patent_app_type] => B1 [patent_app_number] => 09/532886 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 53 [patent_no_of_words] => 11640 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500694.pdf [firstpage_image] =>[orig_patent_app_number] => 09532886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459534 [patent_doc_number] => 06391769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby' [patent_app_type] => B1 [patent_app_number] => 09/525154 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 11214 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391769.pdf [firstpage_image] =>[orig_patent_app_number] => 09525154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1332062 [patent_doc_number] => 06596565 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Chip on board and heat sink attachment methods' [patent_app_type] => B1 [patent_app_number] => 09/511609 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5255 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596565.pdf [firstpage_image] =>[orig_patent_app_number] => 09511609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1535970 [patent_doc_number] => 06337226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor package with supported overhanging upper die' [patent_app_type] => B1 [patent_app_number] => 09/504895 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2125 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337226.pdf [firstpage_image] =>[orig_patent_app_number] => 09504895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645719 [patent_doc_number] => 06472250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method for producing a chip module' [patent_app_type] => B1 [patent_app_number] => 09/494776 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1973 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472250.pdf [firstpage_image] =>[orig_patent_app_number] => 09494776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327832 [patent_doc_number] => 06319851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for packaging semiconductor device having bump electrodes' [patent_app_type] => 1 [patent_app_number] => 9/487165 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 4659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319851.pdf [firstpage_image] =>[orig_patent_app_number] => 487165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565602 [patent_doc_number] => 06376279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'method for manufacturing a semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/482216 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 3123 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376279.pdf [firstpage_image] =>[orig_patent_app_number] => 09482216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645723 [patent_doc_number] => 06472246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Electrostatic discharge protection for integrated circuit sensor passivation' [patent_app_type] => B1 [patent_app_number] => 09/473365 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3796 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472246.pdf [firstpage_image] =>[orig_patent_app_number] => 09473365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580996 [patent_doc_number] => 06423576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package' [patent_app_type] => B1 [patent_app_number] => 09/460175 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423576.pdf [firstpage_image] =>[orig_patent_app_number] => 09460175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6986854 [patent_doc_number] => 20010036686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'METHODS OF FORMING AN INTEGRATED CIRCUIT DEVICE' [patent_app_type] => new [patent_app_number] => 09/449026 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3401 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036686.pdf [firstpage_image] =>[orig_patent_app_number] => 09449026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4328713 [patent_doc_number] => 06312976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method for manufacturing leadless semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/444366 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1960 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312976.pdf [firstpage_image] =>[orig_patent_app_number] => 444366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407977 [patent_doc_number] => 06309916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method of molding plastic semiconductor packages' [patent_app_type] => 1 [patent_app_number] => 9/441115 [patent_app_country] => US [patent_app_date] => 1999-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4731 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309916.pdf [firstpage_image] =>[orig_patent_app_number] => 441115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405047 [patent_doc_number] => 06232151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Power electronic module packaging' [patent_app_type] => 1 [patent_app_number] => 9/431415 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3446 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232151.pdf [firstpage_image] =>[orig_patent_app_number] => 431415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1062736 [patent_doc_number] => 06849480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Surface mount IC stacking method and device' [patent_app_type] => utility [patent_app_number] => 09/427226 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8030 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849480.pdf [firstpage_image] =>[orig_patent_app_number] => 09427226 [rel_patent_id] =>[rel_patent_doc_number] =>)