Search

Nema O. Berezny

Examiner (ID: 9201)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
286
Issued Applications
250
Pending Applications
5
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4326318 [patent_doc_number] => 06319753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor device having lead terminals bent in J-shape' [patent_app_type] => 1 [patent_app_number] => 9/417745 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 4524 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319753.pdf [firstpage_image] =>[orig_patent_app_number] => 417745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417745
Semiconductor device having lead terminals bent in J-shape Oct 13, 1999 Issued
Array ( [id] => 1459255 [patent_doc_number] => 06391684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-21 [patent_title] => 'Lead frame and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/414796 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 46 [patent_no_of_words] => 5737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391684.pdf [firstpage_image] =>[orig_patent_app_number] => 09414796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414796
Lead frame and manufacturing method thereof Oct 7, 1999 Issued
Array ( [id] => 4349939 [patent_doc_number] => 06291269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor bare chip, method of manufacturing semiconductor bare chip and mounting structure of semiconductor bare chip' [patent_app_type] => 1 [patent_app_number] => 9/409896 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3298 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291269.pdf [firstpage_image] =>[orig_patent_app_number] => 409896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409896
Semiconductor bare chip, method of manufacturing semiconductor bare chip and mounting structure of semiconductor bare chip Sep 30, 1999 Issued
Array ( [id] => 1339561 [patent_doc_number] => 06589814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Lead frame chip scale package' [patent_app_type] => B1 [patent_app_number] => 09/399585 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1798 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589814.pdf [firstpage_image] =>[orig_patent_app_number] => 09399585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399585
Lead frame chip scale package Sep 19, 1999 Issued
Array ( [id] => 4309883 [patent_doc_number] => 06316292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Adhesion enhanced semiconductor die for mold compound packaging' [patent_app_type] => 1 [patent_app_number] => 9/394180 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316292.pdf [firstpage_image] =>[orig_patent_app_number] => 394180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394180
Adhesion enhanced semiconductor die for mold compound packaging Sep 9, 1999 Issued
Array ( [id] => 4302393 [patent_doc_number] => 06251766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for improving attachment reliability of semiconductor chips and modules' [patent_app_type] => 1 [patent_app_number] => 9/388755 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4511 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251766.pdf [firstpage_image] =>[orig_patent_app_number] => 388755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388755
Method for improving attachment reliability of semiconductor chips and modules Sep 1, 1999 Issued
Array ( [id] => 1577987 [patent_doc_number] => 06448110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method for fabricating a dual-chip package and package formed' [patent_app_type] => B1 [patent_app_number] => 09/382436 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3377 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448110.pdf [firstpage_image] =>[orig_patent_app_number] => 09382436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382436
Method for fabricating a dual-chip package and package formed Aug 24, 1999 Issued
Array ( [id] => 1150347 [patent_doc_number] => 06774480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method and structure for manufacturing improved yield semiconductor packaged devices' [patent_app_type] => B1 [patent_app_number] => 09/365356 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3176 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774480.pdf [firstpage_image] =>[orig_patent_app_number] => 09365356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365356
Method and structure for manufacturing improved yield semiconductor packaged devices Jul 29, 1999 Issued
Array ( [id] => 4380559 [patent_doc_number] => 06261866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method and apparatus for sealing a chip carrier and lid' [patent_app_type] => 1 [patent_app_number] => 9/364965 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2276 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261866.pdf [firstpage_image] =>[orig_patent_app_number] => 364965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364965
Method and apparatus for sealing a chip carrier and lid Jul 29, 1999 Issued
Array ( [id] => 1494320 [patent_doc_number] => 06342443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate' [patent_app_type] => B1 [patent_app_number] => 09/346735 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2825 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342443.pdf [firstpage_image] =>[orig_patent_app_number] => 09346735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346735
Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate Jul 1, 1999 Issued
Array ( [id] => 1474389 [patent_doc_number] => 06387731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method and apparatus for reducing BGA warpage caused by encapsulation' [patent_app_type] => B1 [patent_app_number] => 09/334045 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3202 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387731.pdf [firstpage_image] =>[orig_patent_app_number] => 09334045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334045
Method and apparatus for reducing BGA warpage caused by encapsulation Jun 14, 1999 Issued
Array ( [id] => 6342695 [patent_doc_number] => 20020034834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'OPTOELECTRONIC ASSEMBLY AND METHOD OF MAKING THE SAME' [patent_app_type] => new [patent_app_number] => 09/334146 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6561 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034834.pdf [firstpage_image] =>[orig_patent_app_number] => 09334146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334146
Optoelectronic assembly and method of making the same Jun 14, 1999 Issued
Array ( [id] => 4267361 [patent_doc_number] => 06306749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Bond pad with pad edge strengthening structure' [patent_app_type] => 1 [patent_app_number] => 9/327874 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5376 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306749.pdf [firstpage_image] =>[orig_patent_app_number] => 327874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327874
Bond pad with pad edge strengthening structure Jun 7, 1999 Issued
Array ( [id] => 4246379 [patent_doc_number] => 06221682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects' [patent_app_type] => 1 [patent_app_number] => 9/321565 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5325 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221682.pdf [firstpage_image] =>[orig_patent_app_number] => 321565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321565
Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects May 27, 1999 Issued
Array ( [id] => 4420503 [patent_doc_number] => 06225206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Flip chip C4 extension structure and process' [patent_app_type] => 1 [patent_app_number] => 9/309405 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9401 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225206.pdf [firstpage_image] =>[orig_patent_app_number] => 309405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309405
Flip chip C4 extension structure and process May 9, 1999 Issued
Array ( [id] => 4408952 [patent_doc_number] => 06300254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Methods of making compliant interfaces and microelectronic packages using same' [patent_app_type] => 1 [patent_app_number] => 9/293005 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 3774 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300254.pdf [firstpage_image] =>[orig_patent_app_number] => 293005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293005
Methods of making compliant interfaces and microelectronic packages using same Apr 15, 1999 Issued
Array ( [id] => 4070371 [patent_doc_number] => 06069024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/291996 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3662 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069024.pdf [firstpage_image] =>[orig_patent_app_number] => 291996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291996
Method for producing a semiconductor device Apr 14, 1999 Issued
Array ( [id] => 4416939 [patent_doc_number] => 06194251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Die positioning in integrated circuit packaging' [patent_app_type] => 1 [patent_app_number] => 9/286555 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1487 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194251.pdf [firstpage_image] =>[orig_patent_app_number] => 286555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286555
Die positioning in integrated circuit packaging Apr 4, 1999 Issued
Array ( [id] => 1113036 [patent_doc_number] => 06803327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Cost effective polymide process to solve passivation extrusion or damage and SOG delminates' [patent_app_type] => B1 [patent_app_number] => 09/285986 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4169 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803327.pdf [firstpage_image] =>[orig_patent_app_number] => 09285986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285986
Cost effective polymide process to solve passivation extrusion or damage and SOG delminates Apr 4, 1999 Issued
Array ( [id] => 4301476 [patent_doc_number] => 06251704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of manufacturing semiconductor devices having solder bumps with reduced cracks' [patent_app_type] => 1 [patent_app_number] => 9/285656 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 9364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251704.pdf [firstpage_image] =>[orig_patent_app_number] => 285656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285656
Method of manufacturing semiconductor devices having solder bumps with reduced cracks Apr 4, 1999 Issued
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