Search

Nga Doan

Examiner (ID: 19180, Phone: (571)270-5356 , Office: P/2817 )

Most Active Art Unit
2813
Art Unit(s)
2817, 2813, 4172
Total Applications
427
Issued Applications
310
Pending Applications
0
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5010950 [patent_doc_number] => 20070281429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/730805 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5403 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281429.pdf [firstpage_image] =>[orig_patent_app_number] => 11730805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730805
Method for fabricating semiconductor device Apr 3, 2007 Abandoned
Array ( [id] => 5472856 [patent_doc_number] => 20090246022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'FIRE FIGHTING PUMP AND ITS OPERATING METHODS' [patent_app_type] => utility [patent_app_number] => 12/374313 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4404 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20090246022.pdf [firstpage_image] =>[orig_patent_app_number] => 12374313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/374313
FIRE FIGHTING PUMP AND ITS OPERATING METHODS Mar 13, 2007 Abandoned
Array ( [id] => 5319801 [patent_doc_number] => 20090057791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP' [patent_app_type] => utility [patent_app_number] => 12/281886 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5818 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057791.pdf [firstpage_image] =>[orig_patent_app_number] => 12281886 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/281886
MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP Mar 11, 2007 Abandoned
Array ( [id] => 326573 [patent_doc_number] => 07514344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Lateral bipolar transistor' [patent_app_type] => utility [patent_app_number] => 11/682126 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 10939 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514344.pdf [firstpage_image] =>[orig_patent_app_number] => 11682126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682126
Lateral bipolar transistor Mar 4, 2007 Issued
Array ( [id] => 4723995 [patent_doc_number] => 20080203536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 11/679971 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203536.pdf [firstpage_image] =>[orig_patent_app_number] => 11679971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679971
BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF Feb 27, 2007 Abandoned
Array ( [id] => 4727416 [patent_doc_number] => 20080206960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'REWORKABLE CHIP STACK' [patent_app_type] => utility [patent_app_number] => 11/679226 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4029 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206960.pdf [firstpage_image] =>[orig_patent_app_number] => 11679226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679226
REWORKABLE CHIP STACK Feb 26, 2007 Abandoned
Array ( [id] => 348819 [patent_doc_number] => 07494935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Method for forming fine pattern of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/679176 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494935.pdf [firstpage_image] =>[orig_patent_app_number] => 11679176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679176
Method for forming fine pattern of semiconductor device Feb 25, 2007 Issued
Array ( [id] => 4870600 [patent_doc_number] => 20080197334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Phase Change Memory Cell with Heater and Method for Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 11/677416 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197334.pdf [firstpage_image] =>[orig_patent_app_number] => 11677416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677416
Phase change memory cell with heater and method for fabricating the same Feb 20, 2007 Issued
Array ( [id] => 4870607 [patent_doc_number] => 20080197341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'METHOD FOR MAKING A MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE' [patent_app_type] => utility [patent_app_number] => 11/675846 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6339 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197341.pdf [firstpage_image] =>[orig_patent_app_number] => 11675846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675846
Method for making a multiple-wavelength opto-electronic device including a superlattice Feb 15, 2007 Issued
Array ( [id] => 4870740 [patent_doc_number] => 20080197474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Semiconductor device package with multi-chips and method of the same' [patent_app_type] => utility [patent_app_number] => 11/707042 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5978 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197474.pdf [firstpage_image] =>[orig_patent_app_number] => 11707042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707042
Semiconductor device package with multi-chips and method of the same Feb 15, 2007 Abandoned
Array ( [id] => 4870765 [patent_doc_number] => 20080197499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'STRUCTURE FOR METAL CAP APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/675296 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197499.pdf [firstpage_image] =>[orig_patent_app_number] => 11675296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675296
STRUCTURE FOR METAL CAP APPLICATIONS Feb 14, 2007 Abandoned
Array ( [id] => 5236585 [patent_doc_number] => 20070128742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'METHOD OF FORMING SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR SUBSTRATE AND SOI SEMICONDUCTOR SUBSTRATE FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 11/673865 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128742.pdf [firstpage_image] =>[orig_patent_app_number] => 11673865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673865
METHOD OF FORMING SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR SUBSTRATE AND SOI SEMICONDUCTOR SUBSTRATE FORMED THEREBY Feb 11, 2007 Abandoned
Array ( [id] => 4813440 [patent_doc_number] => 20080194071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD OF FORMING NON-VOLATILE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/673606 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2442 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194071.pdf [firstpage_image] =>[orig_patent_app_number] => 11673606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673606
Method of forming non-volatile memory cell Feb 11, 2007 Issued
Array ( [id] => 202511 [patent_doc_number] => 07632724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Stressed SOI FET having tensile and compressive device regions' [patent_app_type] => utility [patent_app_number] => 11/673716 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/632/07632724.pdf [firstpage_image] =>[orig_patent_app_number] => 11673716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673716
Stressed SOI FET having tensile and compressive device regions Feb 11, 2007 Issued
Array ( [id] => 4813468 [patent_doc_number] => 20080194099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Method for Integrating Liner Formation in Back End of Line Processing' [patent_app_type] => utility [patent_app_number] => 11/673276 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194099.pdf [firstpage_image] =>[orig_patent_app_number] => 11673276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673276
Method for integrating liner formation in back end of line processing Feb 8, 2007 Issued
Array ( [id] => 4441896 [patent_doc_number] => 07927950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method of fabricating trap type nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/672916 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 51 [patent_no_of_words] => 10936 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/927/07927950.pdf [firstpage_image] =>[orig_patent_app_number] => 11672916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672916
Method of fabricating trap type nonvolatile memory device Feb 7, 2007 Issued
Array ( [id] => 303533 [patent_doc_number] => 07534669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Method and structure to create multiple device widths in FinFET technology in both bulk and SOI' [patent_app_type] => utility [patent_app_number] => 11/671795 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 3247 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534669.pdf [firstpage_image] =>[orig_patent_app_number] => 11671795 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671795
Method and structure to create multiple device widths in FinFET technology in both bulk and SOI Feb 5, 2007 Issued
Array ( [id] => 5101324 [patent_doc_number] => 20070184586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'THIN FILM TRANSISTOR PANEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/670676 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184586.pdf [firstpage_image] =>[orig_patent_app_number] => 11670676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670676
THIN FILM TRANSISTOR PANEL AND METHOD OF MANUFACTURING THE SAME Feb 1, 2007 Abandoned
Array ( [id] => 5236614 [patent_doc_number] => 20070128771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'METHOD AND STRUCTURE FOR FORMING AN INTEGRATED SPATIAL LIGHT MODULATOR' [patent_app_type] => utility [patent_app_number] => 11/670362 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6683 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128771.pdf [firstpage_image] =>[orig_patent_app_number] => 11670362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670362
Method and structure for forming an integrated spatial light modulator Jan 31, 2007 Issued
Array ( [id] => 111733 [patent_doc_number] => 07718540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Pitch reduced patterns relative to photolithography features' [patent_app_type] => utility [patent_app_number] => 11/670296 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11844 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/718/07718540.pdf [firstpage_image] =>[orig_patent_app_number] => 11670296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670296
Pitch reduced patterns relative to photolithography features Jan 31, 2007 Issued
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