
Nga Doan
Examiner (ID: 18754, Phone: (571)270-5356 , Office: P/2817 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 2817, 4172 |
| Total Applications | 427 |
| Issued Applications | 311 |
| Pending Applications | 0 |
| Abandoned Applications | 119 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9418738
[patent_doc_number] => 20140103388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'LIGHT EMITTING DIODE HAVING ELECTRODE PADS'
[patent_app_type] => utility
[patent_app_number] => 14/140950
[patent_app_country] => US
[patent_app_date] => 2013-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7463
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140950
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/140950 | LIGHT EMITTING DIODE HAVING ELECTRODE PADS | Dec 25, 2013 | Abandoned |
Array
(
[id] => 11489417
[patent_doc_number] => 09595489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-14
[patent_title] => 'Semiconductor package with bonding wires of reduced loop inductance'
[patent_app_type] => utility
[patent_app_number] => 14/109618
[patent_app_country] => US
[patent_app_date] => 2013-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 7635
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 345
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14109618
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/109618 | Semiconductor package with bonding wires of reduced loop inductance | Dec 16, 2013 | Issued |
Array
(
[id] => 9406198
[patent_doc_number] => 20140097450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-10
[patent_title] => 'Diffused Junction Termination Structures for Silicon Carbide Devices'
[patent_app_type] => utility
[patent_app_number] => 14/102904
[patent_app_country] => US
[patent_app_date] => 2013-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7138
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102904
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/102904 | Diffused junction termination structures for silicon carbide devices | Dec 10, 2013 | Issued |
Array
(
[id] => 10053423
[patent_doc_number] => 09093305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-28
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/098809
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7078
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14098809
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/098809 | Semiconductor device | Dec 5, 2013 | Issued |
Array
(
[id] => 9380959
[patent_doc_number] => 20140084440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-27
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/090295
[patent_app_country] => US
[patent_app_date] => 2013-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 11940
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090295
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/090295 | Semiconductor device | Nov 25, 2013 | Issued |
Array
(
[id] => 9366619
[patent_doc_number] => 20140076492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS'
[patent_app_type] => utility
[patent_app_number] => 14/084901
[patent_app_country] => US
[patent_app_date] => 2013-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2766
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084901
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/084901 | FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS | Nov 19, 2013 | Abandoned |
Array
(
[id] => 9335077
[patent_doc_number] => 20140061859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-06
[patent_title] => 'STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 14/073611
[patent_app_country] => US
[patent_app_date] => 2013-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11819
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073611
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/073611 | Stacked ESD clamp with reduced variation in clamp voltage | Nov 5, 2013 | Issued |
Array
(
[id] => 9294742
[patent_doc_number] => 20140038376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-06
[patent_title] => 'Method and Apparatus of Forming ESD Protection Device'
[patent_app_type] => utility
[patent_app_number] => 14/058390
[patent_app_country] => US
[patent_app_date] => 2013-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5367
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058390
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/058390 | Method and apparatus of forming ESD protection device | Oct 20, 2013 | Issued |
Array
(
[id] => 11539506
[patent_doc_number] => 09613921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-04
[patent_title] => 'Structure to prevent solder extrusion'
[patent_app_type] => utility
[patent_app_number] => 14/057649
[patent_app_country] => US
[patent_app_date] => 2013-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5667
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057649
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/057649 | Structure to prevent solder extrusion | Oct 17, 2013 | Issued |
Array
(
[id] => 11776135
[patent_doc_number] => 09385087
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Polysilicon resistor structure having modified oxide layer'
[patent_app_type] => utility
[patent_app_number] => 14/057084
[patent_app_country] => US
[patent_app_date] => 2013-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3855
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057084
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/057084 | Polysilicon resistor structure having modified oxide layer | Oct 17, 2013 | Issued |
Array
(
[id] => 10223431
[patent_doc_number] => 20150108424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'Method to Remove Sapphire Substrate'
[patent_app_type] => utility
[patent_app_number] => 14/057053
[patent_app_country] => US
[patent_app_date] => 2013-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5335
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057053
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/057053 | Method to Remove Sapphire Substrate | Oct 17, 2013 | Abandoned |
Array
(
[id] => 11180689
[patent_doc_number] => 09412684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-09
[patent_title] => 'Top exposed semiconductor chip package'
[patent_app_type] => utility
[patent_app_number] => 14/056047
[patent_app_country] => US
[patent_app_date] => 2013-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 30
[patent_no_of_words] => 6756
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056047
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/056047 | Top exposed semiconductor chip package | Oct 16, 2013 | Issued |
Array
(
[id] => 11599887
[patent_doc_number] => 09647065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Bipolar transistor structure having split collector region and method of making the same'
[patent_app_type] => utility
[patent_app_number] => 14/056393
[patent_app_country] => US
[patent_app_date] => 2013-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4687
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056393
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/056393 | Bipolar transistor structure having split collector region and method of making the same | Oct 16, 2013 | Issued |
Array
(
[id] => 9552086
[patent_doc_number] => 08759133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Back panel for flat panel display apparatus, flat panel display apparatus comprising the same, and method of manufacturing the back panel'
[patent_app_type] => utility
[patent_app_number] => 14/054085
[patent_app_country] => US
[patent_app_date] => 2013-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4233
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054085
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/054085 | Back panel for flat panel display apparatus, flat panel display apparatus comprising the same, and method of manufacturing the back panel | Oct 14, 2013 | Issued |
Array
(
[id] => 9460428
[patent_doc_number] => 20140124853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/051451
[patent_app_country] => US
[patent_app_date] => 2013-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 1967
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051451
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/051451 | SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF | Oct 10, 2013 | Abandoned |
Array
(
[id] => 10125294
[patent_doc_number] => 09159660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Semiconductor package structure and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 14/042979
[patent_app_country] => US
[patent_app_date] => 2013-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 23
[patent_no_of_words] => 2592
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042979
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/042979 | Semiconductor package structure and method for making the same | Sep 30, 2013 | Issued |
Array
(
[id] => 9294741
[patent_doc_number] => 20140038375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-06
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/041822
[patent_app_country] => US
[patent_app_date] => 2013-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 7505
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041822
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/041822 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE | Sep 29, 2013 | Abandoned |
Array
(
[id] => 9277926
[patent_doc_number] => 20140027894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/040211
[patent_app_country] => US
[patent_app_date] => 2013-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2378
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040211
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/040211 | RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Sep 26, 2013 | Abandoned |
Array
(
[id] => 9716931
[patent_doc_number] => 20140252629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-11
[patent_title] => 'Self-Aligned Pitch Split for Unidirectional Metal Wiring'
[patent_app_type] => utility
[patent_app_number] => 13/972178
[patent_app_country] => US
[patent_app_date] => 2013-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4109
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972178
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/972178 | Self-aligned pitch split for unidirectional metal wiring | Aug 20, 2013 | Issued |
Array
(
[id] => 11639765
[patent_doc_number] => 09661761
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Carrier substrate and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/965194
[patent_app_country] => US
[patent_app_date] => 2013-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 29
[patent_no_of_words] => 9134
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 374
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965194
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/965194 | Carrier substrate and manufacturing method thereof | Aug 12, 2013 | Issued |