Search

Ngan V. Ngo

Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )

Most Active Art Unit
2503
Art Unit(s)
2818, 2893, 2503, 2811, 2814, 2819
Total Applications
3475
Issued Applications
2900
Pending Applications
46
Abandoned Applications
536

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6955628 [patent_doc_number] => 20050211998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Light active sheet material' [patent_app_type] => utility [patent_app_number] => 10/920010 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17274 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20050211998.pdf [firstpage_image] =>[orig_patent_app_number] => 10920010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920010
Light active sheet material Aug 16, 2004 Issued
Array ( [id] => 613159 [patent_doc_number] => 07148558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Versatile system for limiting mobile charge ingress in SOI semiconductor structures' [patent_app_type] => utility [patent_app_number] => 10/919390 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3097 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148558.pdf [firstpage_image] =>[orig_patent_app_number] => 10919390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/919390
Versatile system for limiting mobile charge ingress in SOI semiconductor structures Aug 16, 2004 Issued
Array ( [id] => 5625479 [patent_doc_number] => 20060263984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Vertical nanotransistor, method for producing the same and memory assembly' [patent_app_type] => utility [patent_app_number] => 10/568230 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1232 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20060263984.pdf [firstpage_image] =>[orig_patent_app_number] => 10568230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/568230
Vertical nanotransistor, method for producing the same and memory assembly Aug 15, 2004 Abandoned
Array ( [id] => 744560 [patent_doc_number] => 07026183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Long-wavelength semiconductor light emitting device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/917900 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4564 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026183.pdf [firstpage_image] =>[orig_patent_app_number] => 10917900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917900
Long-wavelength semiconductor light emitting device and its manufacturing method Aug 12, 2004 Issued
Array ( [id] => 951306 [patent_doc_number] => 06960508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'MOS transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/915818 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2267 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960508.pdf [firstpage_image] =>[orig_patent_app_number] => 10915818 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915818
MOS transistor and method of manufacturing the same Aug 9, 2004 Issued
Array ( [id] => 692039 [patent_doc_number] => 07075159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Horizontal MOS transistor' [patent_app_type] => utility [patent_app_number] => 10/911630 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075159.pdf [firstpage_image] =>[orig_patent_app_number] => 10911630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911630
Horizontal MOS transistor Aug 4, 2004 Issued
Array ( [id] => 422104 [patent_doc_number] => 07274036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Gate shorted to body thin film transistor, manufacturing method thereof, and display including the same' [patent_app_type] => utility [patent_app_number] => 10/910350 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2917 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274036.pdf [firstpage_image] =>[orig_patent_app_number] => 10910350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910350
Gate shorted to body thin film transistor, manufacturing method thereof, and display including the same Aug 3, 2004 Issued
Array ( [id] => 7139972 [patent_doc_number] => 20050116217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Trench type mosgated device with strained layer on trench sidewall' [patent_app_type] => utility [patent_app_number] => 10/911170 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1327 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116217.pdf [firstpage_image] =>[orig_patent_app_number] => 10911170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911170
Trench type mosgated device with strained layer on trench sidewall Aug 3, 2004 Issued
Array ( [id] => 7008356 [patent_doc_number] => 20050062072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Coupled superconducting charge quantum bit device and controlled-not gate using the same' [patent_app_type] => utility [patent_app_number] => 10/910770 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5017 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062072.pdf [firstpage_image] =>[orig_patent_app_number] => 10910770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910770
Coupled superconducting charge quantum bit device and controlled-not gate using the same Aug 3, 2004 Issued
Array ( [id] => 7031080 [patent_doc_number] => 20050029655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/909368 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4264 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20050029655.pdf [firstpage_image] =>[orig_patent_app_number] => 10909368 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909368
Semiconductor device Aug 2, 2004 Abandoned
Array ( [id] => 447723 [patent_doc_number] => 07253501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'High performance metallization cap layer' [patent_app_type] => utility [patent_app_number] => 10/909980 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6056 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253501.pdf [firstpage_image] =>[orig_patent_app_number] => 10909980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909980
High performance metallization cap layer Aug 2, 2004 Issued
Array ( [id] => 5817945 [patent_doc_number] => 20060022258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'MEMORY DEVICE WITH REDUCED CELL AREA' [patent_app_type] => utility [patent_app_number] => 10/910210 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5421 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022258.pdf [firstpage_image] =>[orig_patent_app_number] => 10910210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910210
Memory device with reduced cell area Aug 1, 2004 Issued
Array ( [id] => 5817941 [patent_doc_number] => 20060022254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Strapping word lines of NAND memory devices' [patent_app_type] => utility [patent_app_number] => 10/909716 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4618 [patent_no_of_claims] => 113 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022254.pdf [firstpage_image] =>[orig_patent_app_number] => 10909716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909716
Strapping word lines of NAND memory devices Aug 1, 2004 Issued
Array ( [id] => 7404220 [patent_doc_number] => 20040262622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Double pinned photodiode for CMOS APS and method of formation' [patent_app_type] => new [patent_app_number] => 10/898939 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6187 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262622.pdf [firstpage_image] =>[orig_patent_app_number] => 10898939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898939
Double pinned photodiode for CMOS APS and method of formation Jul 26, 2004 Issued
Array ( [id] => 1015006 [patent_doc_number] => 06894350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'LDMOS transistor capable of attaining high withstand voltage with low on-resistance and having a structure suitable for incorporation with other MOS transistors' [patent_app_type] => utility [patent_app_number] => 10/897089 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 9890 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894350.pdf [firstpage_image] =>[orig_patent_app_number] => 10897089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897089
LDMOS transistor capable of attaining high withstand voltage with low on-resistance and having a structure suitable for incorporation with other MOS transistors Jul 22, 2004 Issued
Array ( [id] => 7405058 [patent_doc_number] => 20040262731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Self-testing printed circuit board comprising electrically programmable three-dimensional memory' [patent_app_type] => new [patent_app_number] => 10/895582 [patent_app_country] => US [patent_app_date] => 2004-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 25554 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262731.pdf [firstpage_image] =>[orig_patent_app_number] => 10895582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895582
Self-testing printed circuit board comprising electrically programmable three-dimensional memory Jul 20, 2004 Issued
Array ( [id] => 7338527 [patent_doc_number] => 20040245593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Backside thinning of image array devices' [patent_app_type] => new [patent_app_number] => 10/891877 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7780 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20040245593.pdf [firstpage_image] =>[orig_patent_app_number] => 10891877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891877
Backside thinning of image array devices Jul 14, 2004 Issued
Array ( [id] => 6975462 [patent_doc_number] => 20050285177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Vertical memory cell and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/878016 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4037 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285177.pdf [firstpage_image] =>[orig_patent_app_number] => 10878016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878016
Vertical memory cell and manufacturing method thereof Jun 28, 2004 Issued
Array ( [id] => 7120338 [patent_doc_number] => 20050012167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Image sensor production method and image sensor' [patent_app_type] => utility [patent_app_number] => 10/878109 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5000 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012167.pdf [firstpage_image] =>[orig_patent_app_number] => 10878109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878109
Image sensor with surface regions of different doping Jun 28, 2004 Issued
Array ( [id] => 754296 [patent_doc_number] => 07023732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Data erasing method, and memory apparatus having data erasing circuit using such method' [patent_app_type] => utility [patent_app_number] => 10/877980 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3251 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023732.pdf [firstpage_image] =>[orig_patent_app_number] => 10877980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877980
Data erasing method, and memory apparatus having data erasing circuit using such method Jun 28, 2004 Issued
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