Search

Ngan V. Ngo

Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )

Most Active Art Unit
2503
Art Unit(s)
2818, 2893, 2503, 2811, 2814, 2819
Total Applications
3475
Issued Applications
2900
Pending Applications
46
Abandoned Applications
536

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6977966 [patent_doc_number] => 20050287684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'APPARATUS AND METHOD FOR DETECTING SOFT BREAKDOWN OF A DIELECTRIC LAYER OF A SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 10/878220 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2519 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287684.pdf [firstpage_image] =>[orig_patent_app_number] => 10878220 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878220
Apparatus and method for detecting soft breakdown of a dielectric layer of a semiconductor wafer Jun 27, 2004 Issued
Array ( [id] => 7273004 [patent_doc_number] => 20040232455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Methods and apparatus for attaching a die to a substrate' [patent_app_type] => new [patent_app_number] => 10/878845 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4814 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232455.pdf [firstpage_image] =>[orig_patent_app_number] => 10878845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878845
Methods and apparatus for attaching a die to a substrate Jun 27, 2004 Issued
Array ( [id] => 7273019 [patent_doc_number] => 20040232470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Memory device having a P+ gate and thin bottom oxide and method of erasing same' [patent_app_type] => new [patent_app_number] => 10/878091 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232470.pdf [firstpage_image] =>[orig_patent_app_number] => 10878091 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878091
Memory device having a P+ gate and thin bottom oxide and method of erasing same Jun 27, 2004 Issued
Array ( [id] => 7404088 [patent_doc_number] => 20040262605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Active matrix organic electro luminescence device panel' [patent_app_type] => new [patent_app_number] => 10/876720 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262605.pdf [firstpage_image] =>[orig_patent_app_number] => 10876720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876720
Active matrix organic electro luminescence device panel Jun 27, 2004 Issued
Array ( [id] => 6975503 [patent_doc_number] => 20050285218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method of forming high voltage devices with retrograde well' [patent_app_type] => utility [patent_app_number] => 10/877450 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285218.pdf [firstpage_image] =>[orig_patent_app_number] => 10877450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877450
Method of forming high voltage devices with retrograde well Jun 24, 2004 Issued
Array ( [id] => 440235 [patent_doc_number] => 07259443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Methods for forming patterns on a filled dielectric material on substrates' [patent_app_type] => utility [patent_app_number] => 10/877739 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259443.pdf [firstpage_image] =>[orig_patent_app_number] => 10877739 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877739
Methods for forming patterns on a filled dielectric material on substrates Jun 24, 2004 Issued
Array ( [id] => 390633 [patent_doc_number] => 07301229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Electrostatic discharge (ESD) protection for integrated circuit packages' [patent_app_type] => utility [patent_app_number] => 10/876980 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3223 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301229.pdf [firstpage_image] =>[orig_patent_app_number] => 10876980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876980
Electrostatic discharge (ESD) protection for integrated circuit packages Jun 24, 2004 Issued
Array ( [id] => 6975449 [patent_doc_number] => 20050285164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Photodetector with polarization state sensor' [patent_app_type] => utility [patent_app_number] => 10/877260 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2795 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285164.pdf [firstpage_image] =>[orig_patent_app_number] => 10877260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877260
Photodetector with polarization state sensor Jun 23, 2004 Issued
Array ( [id] => 4479443 [patent_doc_number] => 07906790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Full spectrum phosphor blends for white light generation with LED chips' [patent_app_type] => utility [patent_app_number] => 10/580973 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5718 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906790.pdf [firstpage_image] =>[orig_patent_app_number] => 10580973 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/580973
Full spectrum phosphor blends for white light generation with LED chips Jun 22, 2004 Issued
Array ( [id] => 7314258 [patent_doc_number] => 20040222453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Memory cell capacitors having an over/under configuration' [patent_app_type] => new [patent_app_number] => 10/870811 [patent_app_country] => US [patent_app_date] => 2004-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7080 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222453.pdf [firstpage_image] =>[orig_patent_app_number] => 10870811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870811
Memory cells having an access transistor with a source/drain region coupled to a capacitor through an extension Jun 16, 2004 Issued
Array ( [id] => 7080536 [patent_doc_number] => 20050045916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Power voltage line layout of semiconductor cells using active area' [patent_app_type] => utility [patent_app_number] => 10/869409 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2138 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045916.pdf [firstpage_image] =>[orig_patent_app_number] => 10869409 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869409
Power voltage line layout of semiconductor cells using active area Jun 15, 2004 Abandoned
Array ( [id] => 465173 [patent_doc_number] => 07238976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Schottky barrier rectifier and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/869718 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/238/07238976.pdf [firstpage_image] =>[orig_patent_app_number] => 10869718 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869718
Schottky barrier rectifier and method of manufacturing the same Jun 14, 2004 Issued
Array ( [id] => 7429392 [patent_doc_number] => 20040266093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method for manufacturing optical bench, optical bench, optical module, silicon wafer substrate in which wiring and groove are formed, and wafer' [patent_app_type] => new [patent_app_number] => 10/863339 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266093.pdf [firstpage_image] =>[orig_patent_app_number] => 10863339 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863339
Method for manufacturing optical bench, optical bench, optical module, silicon wafer substrate in which wiring and groove are formed, and wafer Jun 8, 2004 Issued
Array ( [id] => 7323340 [patent_doc_number] => 20040251466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Electron injection composition for light emitting element, light emitting element, and light emitting device' [patent_app_type] => new [patent_app_number] => 10/862318 [patent_app_country] => US [patent_app_date] => 2004-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6676 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251466.pdf [firstpage_image] =>[orig_patent_app_number] => 10862318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/862318
Electron injection composition for light emitting element, light emitting element, and light emitting device Jun 7, 2004 Issued
Array ( [id] => 964007 [patent_doc_number] => 06949820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Substrate-based chip package' [patent_app_type] => utility [patent_app_number] => 10/859459 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1683 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949820.pdf [firstpage_image] =>[orig_patent_app_number] => 10859459 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859459
Substrate-based chip package Jun 1, 2004 Issued
Array ( [id] => 1005991 [patent_doc_number] => 06906380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Drain side gate trench metal-oxide-semiconductor field effect transistor' [patent_app_type] => utility [patent_app_number] => 10/846339 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 61 [patent_no_of_words] => 11519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906380.pdf [firstpage_image] =>[orig_patent_app_number] => 10846339 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846339
Drain side gate trench metal-oxide-semiconductor field effect transistor May 12, 2004 Issued
Array ( [id] => 7411534 [patent_doc_number] => 20040207009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Power semiconductor device' [patent_app_type] => new [patent_app_number] => 10/843571 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207009.pdf [firstpage_image] =>[orig_patent_app_number] => 10843571 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843571
Power semiconductor device May 11, 2004 Issued
Array ( [id] => 7435034 [patent_doc_number] => 20040210008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Semiconductor device and process for producing the same, and tablet comprising epoxy resin composition' [patent_app_type] => new [patent_app_number] => 10/843339 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9859 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20040210008.pdf [firstpage_image] =>[orig_patent_app_number] => 10843339 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843339
Tablet comprising epoxy resin composition May 11, 2004 Issued
Array ( [id] => 7393732 [patent_doc_number] => 20040173883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'OPTICAL SEMICONDUCTOR ELEMENT UTILIZING OPTICAL TRANSITION BETWEEN ZNO HETEROSTRUCTURE SUB-BANDS' [patent_app_type] => new [patent_app_number] => 10/451378 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3613 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20040173883.pdf [firstpage_image] =>[orig_patent_app_number] => 10451378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/451378
Optical semiconductor element utilizing optical transition between ZnO heterostructure sub-bands May 11, 2004 Issued
Array ( [id] => 7250118 [patent_doc_number] => 20040238899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Integrated semiconductor memory and method for reducing leakage currents in an integrated semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/843318 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20040238899.pdf [firstpage_image] =>[orig_patent_app_number] => 10843318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843318
Integrated semiconductor memory and method for reducing leakage currents in an integrated semiconductor May 11, 2004 Issued
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