Search

Ngan V. Ngo

Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )

Most Active Art Unit
2503
Art Unit(s)
2818, 2893, 2503, 2811, 2814, 2819
Total Applications
3475
Issued Applications
2900
Pending Applications
46
Abandoned Applications
536

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7045705 [patent_doc_number] => 20050250300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Low ohmic layout technique for MOS transistors' [patent_app_type] => utility [patent_app_number] => 10/840602 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2309 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250300.pdf [firstpage_image] =>[orig_patent_app_number] => 10840602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840602
Low ohmic layout technique for MOS transistors May 6, 2004 Issued
Array ( [id] => 7404494 [patent_doc_number] => 20040262656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Memory device' [patent_app_type] => new [patent_app_number] => 10/495000 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10164 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262656.pdf [firstpage_image] =>[orig_patent_app_number] => 10495000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/495000
Memory device May 6, 2004 Abandoned
Array ( [id] => 7061209 [patent_doc_number] => 20050003570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 10/840422 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7788 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003570.pdf [firstpage_image] =>[orig_patent_app_number] => 10840422 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840422
Semiconductor device fabrication method May 6, 2004 Issued
Array ( [id] => 1037839 [patent_doc_number] => 06872991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Low gate-leakage virtual rail circuit' [patent_app_type] => utility [patent_app_number] => 10/840708 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4247 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872991.pdf [firstpage_image] =>[orig_patent_app_number] => 10840708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840708
Low gate-leakage virtual rail circuit May 5, 2004 Issued
Array ( [id] => 793416 [patent_doc_number] => 06982462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Light emitting display device using multi-gate thin film transistor' [patent_app_type] => utility [patent_app_number] => 10/835026 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 50 [patent_no_of_words] => 24751 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982462.pdf [firstpage_image] =>[orig_patent_app_number] => 10835026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835026
Light emitting display device using multi-gate thin film transistor Apr 28, 2004 Issued
Array ( [id] => 7411200 [patent_doc_number] => 20040206956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Thin film transistor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/832544 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 23582 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20040206956.pdf [firstpage_image] =>[orig_patent_app_number] => 10832544 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832544
Thin film transistor device and method of manufacturing the same Apr 26, 2004 Abandoned
Array ( [id] => 7612401 [patent_doc_number] => 06903436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Multiple-time programmable electrical fuse utilizing MOS oxide breakdown' [patent_app_type] => utility [patent_app_number] => 10/833968 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3960 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903436.pdf [firstpage_image] =>[orig_patent_app_number] => 10833968 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/833968
Multiple-time programmable electrical fuse utilizing MOS oxide breakdown Apr 26, 2004 Issued
Array ( [id] => 7296542 [patent_doc_number] => 20040214413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Semiconductor device manufacturing method and film forming method' [patent_app_type] => new [patent_app_number] => 10/829382 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9412 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20040214413.pdf [firstpage_image] =>[orig_patent_app_number] => 10829382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/829382
Semiconductor device manufacturing method and film forming method Apr 21, 2004 Abandoned
Array ( [id] => 759226 [patent_doc_number] => 07015537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor' [patent_app_type] => utility [patent_app_number] => 10/822944 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 11379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015537.pdf [firstpage_image] =>[orig_patent_app_number] => 10822944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822944
Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor Apr 11, 2004 Issued
10/821834 CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME Apr 8, 2004 Abandoned
Array ( [id] => 954119 [patent_doc_number] => 06958534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Power semiconductor module' [patent_app_type] => utility [patent_app_number] => 10/821290 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958534.pdf [firstpage_image] =>[orig_patent_app_number] => 10821290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821290
Power semiconductor module Apr 8, 2004 Issued
Array ( [id] => 935650 [patent_doc_number] => 06975000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method of forming a recessed buried-diffusion device' [patent_app_type] => utility [patent_app_number] => 10/820390 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1502 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975000.pdf [firstpage_image] =>[orig_patent_app_number] => 10820390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820390
Method of forming a recessed buried-diffusion device Apr 7, 2004 Issued
Array ( [id] => 6949887 [patent_doc_number] => 20050224981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Semiconductor processing methods for forming electrical contacts' [patent_app_type] => utility [patent_app_number] => 10/822030 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8000 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224981.pdf [firstpage_image] =>[orig_patent_app_number] => 10822030 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822030
Semiconductor processing methods for forming electrical contacts Apr 7, 2004 Issued
Array ( [id] => 6949684 [patent_doc_number] => 20050224778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Forming self-aligned nano-electrodes' [patent_app_type] => utility [patent_app_number] => 10/819790 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224778.pdf [firstpage_image] =>[orig_patent_app_number] => 10819790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819790
Forming self-aligned nano-electrodes Apr 6, 2004 Issued
Array ( [id] => 6949893 [patent_doc_number] => 20050224987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Structure and method for contact pads having double overcoat-protected bondable metal plugs over copper-metallized integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/820620 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3404 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224987.pdf [firstpage_image] =>[orig_patent_app_number] => 10820620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820620
Structure and method for contact pads having double overcoat-protected bondable metal plugs over copper-metallized integrated circuits Apr 6, 2004 Abandoned
Array ( [id] => 6949789 [patent_doc_number] => 20050224883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Circuit design for increasing charge device model immunity' [patent_app_type] => utility [patent_app_number] => 10/819759 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2429 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224883.pdf [firstpage_image] =>[orig_patent_app_number] => 10819759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819759
Circuit design for increasing charge device model immunity Apr 5, 2004 Abandoned
Array ( [id] => 432624 [patent_doc_number] => 07265398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method and structure for composite trench fill' [patent_app_type] => utility [patent_app_number] => 10/816980 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265398.pdf [firstpage_image] =>[orig_patent_app_number] => 10816980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816980
Method and structure for composite trench fill Apr 1, 2004 Issued
Array ( [id] => 1044098 [patent_doc_number] => 06867461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'ESD protection circuit' [patent_app_type] => utility [patent_app_number] => 10/814128 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3388 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867461.pdf [firstpage_image] =>[orig_patent_app_number] => 10814128 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814128
ESD protection circuit Mar 31, 2004 Issued
Array ( [id] => 645307 [patent_doc_number] => 07119019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Capping of copper structures in hydrophobic ILD using aqueous electro-less bath' [patent_app_type] => utility [patent_app_number] => 10/814592 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1786 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119019.pdf [firstpage_image] =>[orig_patent_app_number] => 10814592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814592
Capping of copper structures in hydrophobic ILD using aqueous electro-less bath Mar 30, 2004 Issued
Array ( [id] => 7406702 [patent_doc_number] => 20040175910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Engineered metal gate electrode' [patent_app_type] => new [patent_app_number] => 10/806117 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175910.pdf [firstpage_image] =>[orig_patent_app_number] => 10806117 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/806117
Engineered metal gate electrode Mar 22, 2004 Issued
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