
Ngan V. Ngo
Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )
| Most Active Art Unit | 2503 |
| Art Unit(s) | 2818, 2893, 2503, 2811, 2814, 2819 |
| Total Applications | 3475 |
| Issued Applications | 2900 |
| Pending Applications | 46 |
| Abandoned Applications | 536 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 774744
[patent_doc_number] => 07002181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Thin film transistor and use of same'
[patent_app_type] => utility
[patent_app_number] => 10/765793
[patent_app_country] => US
[patent_app_date] => 2004-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 5712
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/002/07002181.pdf
[firstpage_image] =>[orig_patent_app_number] => 10765793
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765793 | Thin film transistor and use of same | Jan 26, 2004 | Issued |
Array
(
[id] => 993981
[patent_doc_number] => 06917082
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-07-12
[patent_title] => 'Gate-body cross-link circuitry for metal-oxide-semiconductor transistor circuits'
[patent_app_type] => utility
[patent_app_number] => 10/764840
[patent_app_country] => US
[patent_app_date] => 2004-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 4768
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/917/06917082.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764840
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764840 | Gate-body cross-link circuitry for metal-oxide-semiconductor transistor circuits | Jan 25, 2004 | Issued |
Array
(
[id] => 7183244
[patent_doc_number] => 20050161747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'THIN FILM PHASE-CHANGE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 10/764750
[patent_app_country] => US
[patent_app_date] => 2004-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6344
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20050161747.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764750
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764750 | Thin film phase-change memory | Jan 25, 2004 | Issued |
Array
(
[id] => 951586
[patent_doc_number] => 06960791
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-01
[patent_title] => 'Optical semiconductor apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/764640
[patent_app_country] => US
[patent_app_date] => 2004-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 5361
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/960/06960791.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764640
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764640 | Optical semiconductor apparatus | Jan 25, 2004 | Issued |
Array
(
[id] => 7335115
[patent_doc_number] => 20040189353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage'
[patent_app_type] => new
[patent_app_number] => 10/762340
[patent_app_country] => US
[patent_app_date] => 2004-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9578
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20040189353.pdf
[firstpage_image] =>[orig_patent_app_number] => 10762340
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/762340 | Semiconductor device capable of avoiding latchup breakdown resulting from negative varation of floating offset voltage | Jan 22, 2004 | Issued |
Array
(
[id] => 963645
[patent_doc_number] => 06949457
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'Barrier enhancement'
[patent_app_type] => utility
[patent_app_number] => 10/761540
[patent_app_country] => US
[patent_app_date] => 2004-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 9
[patent_no_of_words] => 3318
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949457.pdf
[firstpage_image] =>[orig_patent_app_number] => 10761540
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/761540 | Barrier enhancement | Jan 20, 2004 | Issued |
Array
(
[id] => 988387
[patent_doc_number] => 06921942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-26
[patent_title] => 'Structure of a lateral diffusion MOS transistor in widespread use as a power control device'
[patent_app_type] => utility
[patent_app_number] => 10/760450
[patent_app_country] => US
[patent_app_date] => 2004-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 5765
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/921/06921942.pdf
[firstpage_image] =>[orig_patent_app_number] => 10760450
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/760450 | Structure of a lateral diffusion MOS transistor in widespread use as a power control device | Jan 20, 2004 | Issued |
Array
(
[id] => 7411435
[patent_doc_number] => 20040206995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/760499
[patent_app_country] => US
[patent_app_date] => 2004-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5657
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20040206995.pdf
[firstpage_image] =>[orig_patent_app_number] => 10760499
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/760499 | Semiconductor device comprising a capacitor using a ferroelectric material | Jan 20, 2004 | Issued |
Array
(
[id] => 7039558
[patent_doc_number] => 20050158957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'CREATING SHALLOW JUNCTION TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 10/761550
[patent_app_country] => US
[patent_app_date] => 2004-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1597
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158957.pdf
[firstpage_image] =>[orig_patent_app_number] => 10761550
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/761550 | Creating shallow junction transistors | Jan 20, 2004 | Issued |
Array
(
[id] => 7120309
[patent_doc_number] => 20050012138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 10/757438
[patent_app_country] => US
[patent_app_date] => 2004-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6626
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012138.pdf
[firstpage_image] =>[orig_patent_app_number] => 10757438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/757438 | Nonvolatile semiconductor memory device | Jan 14, 2004 | Abandoned |
Array
(
[id] => 1093931
[patent_doc_number] => 06825533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Inverted staggered thin film transistor with etch stop layer and method of making same'
[patent_app_type] => B2
[patent_app_number] => 10/756356
[patent_app_country] => US
[patent_app_date] => 2004-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5297
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/825/06825533.pdf
[firstpage_image] =>[orig_patent_app_number] => 10756356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/756356 | Inverted staggered thin film transistor with etch stop layer and method of making same | Jan 13, 2004 | Issued |
Array
(
[id] => 1006043
[patent_doc_number] => 06906400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'SiGe strain relaxed buffer for high mobility devices and a method of fabricating it'
[patent_app_type] => utility
[patent_app_number] => 10/756840
[patent_app_country] => US
[patent_app_date] => 2004-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4388
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/906/06906400.pdf
[firstpage_image] =>[orig_patent_app_number] => 10756840
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/756840 | SiGe strain relaxed buffer for high mobility devices and a method of fabricating it | Jan 12, 2004 | Issued |
Array
(
[id] => 724488
[patent_doc_number] => 07045445
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-16
[patent_title] => 'Method for fabricating semiconductor device by using PECYCLE-CVD process'
[patent_app_type] => utility
[patent_app_number] => 10/740139
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 2353
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/045/07045445.pdf
[firstpage_image] =>[orig_patent_app_number] => 10740139
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/740139 | Method for fabricating semiconductor device by using PECYCLE-CVD process | Dec 17, 2003 | Issued |
Array
(
[id] => 7393422
[patent_doc_number] => 20040173830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Nonvolatile semiconductor memory device with stable ferroelectric capacitor'
[patent_app_type] => new
[patent_app_number] => 10/736788
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 18345
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20040173830.pdf
[firstpage_image] =>[orig_patent_app_number] => 10736788
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/736788 | Nonvolatile semiconductor memory device with stable ferroelectric capacitor | Dec 16, 2003 | Issued |
Array
(
[id] => 1035067
[patent_doc_number] => 06876040
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Dense SRAM cells with selective SOI'
[patent_app_type] => utility
[patent_app_number] => 10/735169
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3566
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/876/06876040.pdf
[firstpage_image] =>[orig_patent_app_number] => 10735169
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735169 | Dense SRAM cells with selective SOI | Dec 11, 2003 | Issued |
Array
(
[id] => 7169225
[patent_doc_number] => 20050121775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'DEVICE AND SYSTEM FOR HEAT SPREADER WITH CONTROLLED THERMAL EXPANSION'
[patent_app_type] => utility
[patent_app_number] => 10/726558
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5656
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20050121775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726558
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726558 | Device and system for heat spreader with controlled thermal expansion | Dec 3, 2003 | Issued |
Array
(
[id] => 6937690
[patent_doc_number] => 20050111251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Memory cell structure'
[patent_app_type] => utility
[patent_app_number] => 10/723331
[patent_app_country] => US
[patent_app_date] => 2003-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5246
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20050111251.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723331 | Memory cell structure | Nov 25, 2003 | Issued |
Array
(
[id] => 7049599
[patent_doc_number] => 20050185486
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2005-08-25
[patent_title] => 'Ferroelectric memory devices including protection adhesion layers and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 10/721480
[patent_app_country] => US
[patent_app_date] => 2003-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4367
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A9/0185/20050185486.pdf
[firstpage_image] =>[orig_patent_app_number] => 10721480
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/721480 | Ferroelectric memory devices including protection adhesion layers and methods of forming the same | Nov 24, 2003 | Abandoned |
Array
(
[id] => 790530
[patent_doc_number] => 06984550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-10
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/718584
[patent_app_country] => US
[patent_app_date] => 2003-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 29
[patent_no_of_words] => 15576
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/984/06984550.pdf
[firstpage_image] =>[orig_patent_app_number] => 10718584
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718584 | Semiconductor device and manufacturing method thereof | Nov 23, 2003 | Issued |
Array
(
[id] => 6915511
[patent_doc_number] => 20050093072
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'METHOD OF ASSESSING POTENTIAL FOR CHARGING DAMAGE IN SOI DESIGNS AND STRUCTURES FOR ELIMINATING POTENTIAL FOR DAMAGE'
[patent_app_type] => utility
[patent_app_number] => 10/605888
[patent_app_country] => US
[patent_app_date] => 2003-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2762
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20050093072.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605888
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605888 | Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage | Nov 3, 2003 | Issued |