
Ngan V. Ngo
Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )
| Most Active Art Unit | 2503 |
| Art Unit(s) | 2818, 2893, 2503, 2811, 2814, 2819 |
| Total Applications | 3475 |
| Issued Applications | 2900 |
| Pending Applications | 46 |
| Abandoned Applications | 536 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1253903
[patent_doc_number] => 06666481
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'Shunt connection to emitter'
[patent_app_type] => B1
[patent_app_number] => 10/262728
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4995
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/666/06666481.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262728
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262728 | Shunt connection to emitter | Sep 30, 2002 | Issued |
Array
(
[id] => 1180372
[patent_doc_number] => 06744112
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-01
[patent_title] => 'Multiple chip guard rings for integrated circuit and chip guard ring interconnect'
[patent_app_type] => B2
[patent_app_number] => 10/261819
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2826
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/744/06744112.pdf
[firstpage_image] =>[orig_patent_app_number] => 10261819
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/261819 | Multiple chip guard rings for integrated circuit and chip guard ring interconnect | Sep 30, 2002 | Issued |
Array
(
[id] => 6837184
[patent_doc_number] => 20030034524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-20
[patent_title] => 'Semiconductor device and method of producing the same'
[patent_app_type] => new
[patent_app_number] => 10/260656
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10013
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20030034524.pdf
[firstpage_image] =>[orig_patent_app_number] => 10260656
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/260656 | Semiconductor device and method of producing the same | Sep 30, 2002 | Issued |
Array
(
[id] => 7623553
[patent_doc_number] => 06686612
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-03
[patent_title] => 'Thyristor-based device adapted to inhibit parasitic current'
[patent_app_type] => B1
[patent_app_number] => 10/263382
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5730
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686612.pdf
[firstpage_image] =>[orig_patent_app_number] => 10263382
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263382 | Thyristor-based device adapted to inhibit parasitic current | Sep 30, 2002 | Issued |
Array
(
[id] => 1390979
[patent_doc_number] => 06552386
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Scalable split-gate flash memory cell structure and its contactless flash memory arrays'
[patent_app_type] => B1
[patent_app_number] => 10/262200
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 7840
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 474
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/552/06552386.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262200
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262200 | Scalable split-gate flash memory cell structure and its contactless flash memory arrays | Sep 29, 2002 | Issued |
Array
(
[id] => 1321424
[patent_doc_number] => 06605838
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-12
[patent_title] => 'Process flow for thick isolation collar with reduced length'
[patent_app_type] => B1
[patent_app_number] => 10/261219
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5092
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/605/06605838.pdf
[firstpage_image] =>[orig_patent_app_number] => 10261219
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/261219 | Process flow for thick isolation collar with reduced length | Sep 29, 2002 | Issued |
Array
(
[id] => 712200
[patent_doc_number] => 07057240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Semiconductor circuit, especially for ignition purposes, and the use of the same'
[patent_app_type] => utility
[patent_app_number] => 10/433848
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6485
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/057/07057240.pdf
[firstpage_image] =>[orig_patent_app_number] => 10433848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/433848 | Semiconductor circuit, especially for ignition purposes, and the use of the same | Sep 29, 2002 | Issued |
Array
(
[id] => 1288445
[patent_doc_number] => 06639263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-28
[patent_title] => 'Semiconductor device with copper wiring connected to storage capacitor'
[patent_app_type] => B2
[patent_app_number] => 10/255714
[patent_app_country] => US
[patent_app_date] => 2002-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7265
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/639/06639263.pdf
[firstpage_image] =>[orig_patent_app_number] => 10255714
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255714 | Semiconductor device with copper wiring connected to storage capacitor | Sep 26, 2002 | Issued |
Array
(
[id] => 1136373
[patent_doc_number] => 06784491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'MOS devices with reduced fringing capacitance'
[patent_app_type] => B2
[patent_app_number] => 10/256978
[patent_app_country] => US
[patent_app_date] => 2002-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1832
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/784/06784491.pdf
[firstpage_image] =>[orig_patent_app_number] => 10256978
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/256978 | MOS devices with reduced fringing capacitance | Sep 26, 2002 | Issued |
Array
(
[id] => 730173
[patent_doc_number] => 07042085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Method for packaging electronic modules and multiple chip packaging'
[patent_app_type] => utility
[patent_app_number] => 10/492269
[patent_app_country] => US
[patent_app_date] => 2002-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3548
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/042/07042085.pdf
[firstpage_image] =>[orig_patent_app_number] => 10492269
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/492269 | Method for packaging electronic modules and multiple chip packaging | Sep 25, 2002 | Issued |
Array
(
[id] => 1246670
[patent_doc_number] => 06677657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-13
[patent_title] => 'High-voltage periphery'
[patent_app_type] => B2
[patent_app_number] => 10/255279
[patent_app_country] => US
[patent_app_date] => 2002-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2527
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/677/06677657.pdf
[firstpage_image] =>[orig_patent_app_number] => 10255279
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255279 | High-voltage periphery | Sep 25, 2002 | Issued |
Array
(
[id] => 6671863
[patent_doc_number] => 20030057466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/254399
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4261
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20030057466.pdf
[firstpage_image] =>[orig_patent_app_number] => 10254399
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/254399 | Capacitor element having a contact hole structure in an electrode structure | Sep 24, 2002 | Issued |
Array
(
[id] => 1150015
[patent_doc_number] => 06774438
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Semiconductor integrated circuit device including an ESD protection circuit with an improved ESD protection capability for input or output circuit protection'
[patent_app_type] => B2
[patent_app_number] => 10/252709
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7001
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/774/06774438.pdf
[firstpage_image] =>[orig_patent_app_number] => 10252709
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/252709 | Semiconductor integrated circuit device including an ESD protection circuit with an improved ESD protection capability for input or output circuit protection | Sep 23, 2002 | Issued |
Array
(
[id] => 6727651
[patent_doc_number] => 20030183841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/252568
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4415
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20030183841.pdf
[firstpage_image] =>[orig_patent_app_number] => 10252568
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/252568 | Insulated high speed semiconductor switching device | Sep 23, 2002 | Issued |
Array
(
[id] => 1306054
[patent_doc_number] => 06621135
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'Microrelays and microrelay fabrication and operating methods'
[patent_app_type] => B1
[patent_app_number] => 10/253728
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4001
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/621/06621135.pdf
[firstpage_image] =>[orig_patent_app_number] => 10253728
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/253728 | Microrelays and microrelay fabrication and operating methods | Sep 23, 2002 | Issued |
Array
(
[id] => 1318830
[patent_doc_number] => 06608331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-19
[patent_title] => 'Assembly for a thin-film optical device, organic electroluminescent display device and method of manufacturing same'
[patent_app_type] => B2
[patent_app_number] => 10/247928
[patent_app_country] => US
[patent_app_date] => 2002-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3776
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/608/06608331.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247928
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247928 | Assembly for a thin-film optical device, organic electroluminescent display device and method of manufacturing same | Sep 19, 2002 | Issued |
Array
(
[id] => 6671877
[patent_doc_number] => 20030057480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Voltage-controlled vertical bidirectional monolithic switch'
[patent_app_type] => new
[patent_app_number] => 10/246918
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2867
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20030057480.pdf
[firstpage_image] =>[orig_patent_app_number] => 10246918
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/246918 | Voltage-controlled vertical bidirectional monolithic switch | Sep 18, 2002 | Issued |
Array
(
[id] => 634542
[patent_doc_number] => 07129555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Magnetic memory with write inhibit selection and the writing method for same'
[patent_app_type] => utility
[patent_app_number] => 10/490490
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 4419
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129555.pdf
[firstpage_image] =>[orig_patent_app_number] => 10490490
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/490490 | Magnetic memory with write inhibit selection and the writing method for same | Sep 18, 2002 | Issued |
Array
(
[id] => 6646941
[patent_doc_number] => 20030075759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Semiconductor device and its manufacturing method'
[patent_app_type] => new
[patent_app_number] => 10/246468
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5230
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20030075759.pdf
[firstpage_image] =>[orig_patent_app_number] => 10246468
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/246468 | Trench-gate semiconductor device | Sep 18, 2002 | Issued |
Array
(
[id] => 7191189
[patent_doc_number] => 20050040433
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same'
[patent_app_type] => utility
[patent_app_number] => 10/490491
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4739
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20050040433.pdf
[firstpage_image] =>[orig_patent_app_number] => 10490491
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/490491 | Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same | Sep 18, 2002 | Issued |