
Ngan V. Ngo
Examiner (ID: 3559, Phone: (571)272-1711 , Office: P/2819 )
| Most Active Art Unit | 2503 |
| Art Unit(s) | 2818, 2893, 2503, 2811, 2814, 2819 |
| Total Applications | 3475 |
| Issued Applications | 2900 |
| Pending Applications | 46 |
| Abandoned Applications | 536 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1330635
[patent_doc_number] => 06600209
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'Mesh capacitor structure in an integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 10/251558
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2559
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/600/06600209.pdf
[firstpage_image] =>[orig_patent_app_number] => 10251558
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/251558 | Mesh capacitor structure in an integrated circuit | Sep 18, 2002 | Issued |
Array
(
[id] => 935648
[patent_doc_number] => 06974998
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-13
[patent_title] => 'Field effect transistor with corner diffusions for reduced leakage'
[patent_app_type] => utility
[patent_app_number] => 10/247218
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 30
[patent_no_of_words] => 6681
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/974/06974998.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247218
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247218 | Field effect transistor with corner diffusions for reduced leakage | Sep 18, 2002 | Issued |
Array
(
[id] => 1254312
[patent_doc_number] => 06670686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Integrated sound transmitter and receiver, and corresponding method for making same'
[patent_app_type] => B2
[patent_app_number] => 10/149088
[patent_app_country] => US
[patent_app_date] => 2002-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3607
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/670/06670686.pdf
[firstpage_image] =>[orig_patent_app_number] => 10149088
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/149088 | Integrated sound transmitter and receiver, and corresponding method for making same | Sep 15, 2002 | Issued |
Array
(
[id] => 1152908
[patent_doc_number] => 06770918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies'
[patent_app_type] => B2
[patent_app_number] => 10/238699
[patent_app_country] => US
[patent_app_date] => 2002-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 9211
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/770/06770918.pdf
[firstpage_image] =>[orig_patent_app_number] => 10238699
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/238699 | Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies | Sep 9, 2002 | Issued |
Array
(
[id] => 7235271
[patent_doc_number] => 20040256710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Device with power semiconductor components for controlling the power of high currents and use of said device'
[patent_app_type] => new
[patent_app_number] => 10/491129
[patent_app_country] => US
[patent_app_date] => 2004-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6377
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20040256710.pdf
[firstpage_image] =>[orig_patent_app_number] => 10491129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/491129 | Device with power semiconductor components for controlling the power of high currents and use of said device | Sep 9, 2002 | Issued |
Array
(
[id] => 7264189
[patent_doc_number] => 20040242022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Production method for semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/488243
[patent_app_country] => US
[patent_app_date] => 2004-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3826
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20040242022.pdf
[firstpage_image] =>[orig_patent_app_number] => 10488243
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/488243 | Production method for semiconductor device | Sep 9, 2002 | Issued |
Array
(
[id] => 1229909
[patent_doc_number] => 06696709
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-24
[patent_title] => 'Low voltage protection module'
[patent_app_type] => B2
[patent_app_number] => 10/235444
[patent_app_country] => US
[patent_app_date] => 2002-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 7546
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/696/06696709.pdf
[firstpage_image] =>[orig_patent_app_number] => 10235444
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/235444 | Low voltage protection module | Sep 4, 2002 | Issued |
Array
(
[id] => 1395847
[patent_doc_number] => 06548867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-15
[patent_title] => 'Semiconductor device having thin film transistor for supplying current to driven element'
[patent_app_type] => B2
[patent_app_number] => 10/233976
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4820
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548867.pdf
[firstpage_image] =>[orig_patent_app_number] => 10233976
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233976 | Semiconductor device having thin film transistor for supplying current to driven element | Sep 2, 2002 | Issued |
Array
(
[id] => 6647067
[patent_doc_number] => 20030075775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Circuit having make-link type fuse and semiconductor device having the same'
[patent_app_type] => new
[patent_app_number] => 10/232338
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4604
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20030075775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232338
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232338 | Circuit having make-link type fuse and semiconductor device having the same | Aug 29, 2002 | Issued |
Array
(
[id] => 1284163
[patent_doc_number] => 06642539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Epitaxial template and barrier for the integration of functional thin film metal oxide heterostructures on silicon'
[patent_app_type] => B2
[patent_app_number] => 10/231401
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 9005
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642539.pdf
[firstpage_image] =>[orig_patent_app_number] => 10231401
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/231401 | Epitaxial template and barrier for the integration of functional thin film metal oxide heterostructures on silicon | Aug 28, 2002 | Issued |
Array
(
[id] => 1254295
[patent_doc_number] => 06670682
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-30
[patent_title] => 'Multilayered doped conductor'
[patent_app_type] => B1
[patent_app_number] => 10/230948
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 7119
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/670/06670682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10230948
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/230948 | Multilayered doped conductor | Aug 28, 2002 | Issued |
Array
(
[id] => 6816123
[patent_doc_number] => 20030067081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-10
[patent_title] => 'Digit line architecture for dynamic memory'
[patent_app_type] => new
[patent_app_number] => 10/232781
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 17846
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20030067081.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232781
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232781 | Digitline architecture for dynamic memory | Aug 27, 2002 | Issued |
Array
(
[id] => 6816085
[patent_doc_number] => 20030067043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-10
[patent_title] => 'Three-dimensional memory'
[patent_app_type] => new
[patent_app_number] => 10/230648
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 25388
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20030067043.pdf
[firstpage_image] =>[orig_patent_app_number] => 10230648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/230648 | Three-dimensional memory | Aug 27, 2002 | Issued |
Array
(
[id] => 1315930
[patent_doc_number] => 06611011
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Memory cell array divided into a plurality of subarrays arranged in matrix form'
[patent_app_type] => B2
[patent_app_number] => 10/228079
[patent_app_country] => US
[patent_app_date] => 2002-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3089
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/611/06611011.pdf
[firstpage_image] =>[orig_patent_app_number] => 10228079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/228079 | Memory cell array divided into a plurality of subarrays arranged in matrix form | Aug 26, 2002 | Issued |
Array
(
[id] => 7031104
[patent_doc_number] => 20050029666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Semiconductor device structural body and electronic device'
[patent_app_type] => utility
[patent_app_number] => 10/487990
[patent_app_country] => US
[patent_app_date] => 2002-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 34728
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20050029666.pdf
[firstpage_image] =>[orig_patent_app_number] => 10487990
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/487990 | Semiconductor device structural body and electronic device | Aug 26, 2002 | Abandoned |
Array
(
[id] => 1197777
[patent_doc_number] => 06727553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-27
[patent_title] => 'Semiconductor device including SOI substrate'
[patent_app_type] => B2
[patent_app_number] => 10/225138
[patent_app_country] => US
[patent_app_date] => 2002-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 7218
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/727/06727553.pdf
[firstpage_image] =>[orig_patent_app_number] => 10225138
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/225138 | Semiconductor device including SOI substrate | Aug 21, 2002 | Issued |
Array
(
[id] => 6776705
[patent_doc_number] => 20030047785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-13
[patent_title] => 'THIN FILM TRANSISTOR AND MATRIX DISPLAY DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/224879
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8961
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20030047785.pdf
[firstpage_image] =>[orig_patent_app_number] => 10224879
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/224879 | Thin film transistor and matrix display device | Aug 20, 2002 | Issued |
Array
(
[id] => 1189881
[patent_doc_number] => 06734505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Thin film transistor and use of same'
[patent_app_type] => B2
[patent_app_number] => 10/222339
[patent_app_country] => US
[patent_app_date] => 2002-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 5683
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/734/06734505.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222339
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222339 | Thin film transistor and use of same | Aug 14, 2002 | Issued |
Array
(
[id] => 1276705
[patent_doc_number] => 06649950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-18
[patent_title] => 'Active pixel having reduced dark current in a CMOS image sensor'
[patent_app_type] => B2
[patent_app_number] => 10/218762
[patent_app_country] => US
[patent_app_date] => 2002-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3137
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/649/06649950.pdf
[firstpage_image] =>[orig_patent_app_number] => 10218762
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/218762 | Active pixel having reduced dark current in a CMOS image sensor | Aug 13, 2002 | Issued |
Array
(
[id] => 680989
[patent_doc_number] => 07084423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'
[patent_app_type] => utility
[patent_app_number] => 10/217758
[patent_app_country] => US
[patent_app_date] => 2002-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 10230
[patent_no_of_claims] => 69
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/084/07084423.pdf
[firstpage_image] =>[orig_patent_app_number] => 10217758
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/217758 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Aug 11, 2002 | Issued |