Search

Ngan V. Ngo

Examiner (ID: 772, Phone: (571)272-1711 , Office: P/2819 )

Most Active Art Unit
2503
Art Unit(s)
2819, 2818, 2814, 2811, 2893, 2503
Total Applications
3475
Issued Applications
2900
Pending Applications
46
Abandoned Applications
536

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13043047 [patent_doc_number] => 10043663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Enhanced defect reduction for heteroepitaxy by seed shape engineering [patent_app_type] => utility [patent_app_number] => 15/395805 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395805 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395805
Enhanced defect reduction for heteroepitaxy by seed shape engineering Dec 29, 2016 Issued
Array ( [id] => 11718295 [patent_doc_number] => 20170186794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DIELECTRIC MIRROR BASED MULTISPECTRAL FILTER ARRAY' [patent_app_type] => utility [patent_app_number] => 15/388543 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/388543
Dielectric mirror based multispectral filter array Dec 21, 2016 Issued
Array ( [id] => 11890978 [patent_doc_number] => 09761543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Integrated circuits with thermal isolation and temperature regulation' [patent_app_type] => utility [patent_app_number] => 15/385098 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385098
Integrated circuits with thermal isolation and temperature regulation Dec 19, 2016 Issued
Array ( [id] => 11732788 [patent_doc_number] => 20170194231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'BALL GRID ARRAY PACKAGE WITH PROTECTIVE CIRCUITRY LAYOUT AND A SUBSTRATE UTILIZED IN THE PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/385320 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385320
Ball grid array package with protective circuitry layout and a substrate utilized in the package Dec 19, 2016 Issued
Array ( [id] => 11687404 [patent_doc_number] => 09685455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-20 [patent_title] => 'Method of manufacturing semiconductor device having 3D structure' [patent_app_type] => utility [patent_app_number] => 15/385133 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 9041 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385133
Method of manufacturing semiconductor device having 3D structure Dec 19, 2016 Issued
Array ( [id] => 11718294 [patent_doc_number] => 20170186793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'METAL MIRROR BASED MULTISPECTRAL FILTER ARRAY' [patent_app_type] => utility [patent_app_number] => 15/385240 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385240 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385240
Metal mirror based multispectral filter array Dec 19, 2016 Issued
Array ( [id] => 11855074 [patent_doc_number] => 20170229566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'SEMICONDUCTOR DEVICE, POWER-SUPPLY DEVICE, AND AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 15/385135 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385135
SEMICONDUCTOR DEVICE, POWER-SUPPLY DEVICE, AND AMPLIFIER Dec 19, 2016 Abandoned
Array ( [id] => 14252461 [patent_doc_number] => 10276437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Contact structure of gate structure [patent_app_type] => utility [patent_app_number] => 15/384446 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384446 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384446
Contact structure of gate structure Dec 19, 2016 Issued
Array ( [id] => 11669779 [patent_doc_number] => 20170158499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'LASER BEAM DEFLECTION FOR TARGETED ENERGY DEPOSITION' [patent_app_type] => utility [patent_app_number] => 15/371659 [patent_app_country] => US [patent_app_date] => 2016-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4797 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15371659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/371659
Laser beam deflection for targeted energy deposition Dec 6, 2016 Issued
Array ( [id] => 12175134 [patent_doc_number] => 09893282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Methods of forming resistive memory elements' [patent_app_type] => utility [patent_app_number] => 15/369427 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/369427
Methods of forming resistive memory elements Dec 4, 2016 Issued
Array ( [id] => 12115047 [patent_doc_number] => 09871042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Semiconductor device having fin-type patterns' [patent_app_type] => utility [patent_app_number] => 15/368723 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 20458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/368723
Semiconductor device having fin-type patterns Dec 4, 2016 Issued
Array ( [id] => 12554031 [patent_doc_number] => 10014234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device comprising a die seal including long via lines [patent_app_type] => utility [patent_app_number] => 15/367888 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367888
Semiconductor device comprising a die seal including long via lines Dec 1, 2016 Issued
Array ( [id] => 11911239 [patent_doc_number] => 09780060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Packaged IC with solderable sidewalls' [patent_app_type] => utility [patent_app_number] => 15/368413 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 3597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/368413
Packaged IC with solderable sidewalls Dec 1, 2016 Issued
Array ( [id] => 12102235 [patent_doc_number] => 09859335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Semiconductor device having memory cell structure' [patent_app_type] => utility [patent_app_number] => 15/367690 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4163 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367690
Semiconductor device having memory cell structure Dec 1, 2016 Issued
Array ( [id] => 11517802 [patent_doc_number] => 20170084877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/364498 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6318 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364498
Display device Nov 29, 2016 Issued
Array ( [id] => 11847806 [patent_doc_number] => 09735367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Light emitting diode' [patent_app_type] => utility [patent_app_number] => 15/361588 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361588
Light emitting diode Nov 27, 2016 Issued
Array ( [id] => 11710555 [patent_doc_number] => 20170179054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Semiconductor Device Structure Comprising a Plurality of Metal Oxide Fibers and Method for Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/362654 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/362654
Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same Nov 27, 2016 Issued
Array ( [id] => 11925532 [patent_doc_number] => 09793119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Method for structuring a substrate using a protection layer as a mask' [patent_app_type] => utility [patent_app_number] => 15/347835 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 58 [patent_no_of_words] => 25795 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/347835
Method for structuring a substrate using a protection layer as a mask Nov 9, 2016 Issued
Array ( [id] => 11911271 [patent_doc_number] => 09780091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Fin pitch scaling for high voltage devices and low voltage devices on the same wafer' [patent_app_type] => utility [patent_app_number] => 15/345595 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345595
Fin pitch scaling for high voltage devices and low voltage devices on the same wafer Nov 7, 2016 Issued
Array ( [id] => 11460129 [patent_doc_number] => 20170054035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/342268 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342268
Electrostatically enhanced fins field effect transistors Nov 2, 2016 Issued
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