Search

Ngoc V. Dinh

Examiner (ID: 15760)

Most Active Art Unit
2187
Art Unit(s)
2188, 2189, 2187, 2185
Total Applications
287
Issued Applications
256
Pending Applications
5
Abandoned Applications
26

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6746626 [patent_doc_number] => 20030023809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Methods and arrangements for improved stripe-based processing' [patent_app_type] => new [patent_app_number] => 09/808648 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8540 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023809.pdf [firstpage_image] =>[orig_patent_app_number] => 09808648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808648
Methods and arrangements for improved stripe-based processing Mar 13, 2001 Issued
Array ( [id] => 1124900 [patent_doc_number] => 06799254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Memory manager for a common memory' [patent_app_type] => B2 [patent_app_number] => 09/808711 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3570 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799254.pdf [firstpage_image] =>[orig_patent_app_number] => 09808711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808711
Memory manager for a common memory Mar 13, 2001 Issued
Array ( [id] => 5848379 [patent_doc_number] => 20020133673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'System and method for caching data based on identity of requestor' [patent_app_type] => new [patent_app_number] => 09/805663 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3714 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133673.pdf [firstpage_image] =>[orig_patent_app_number] => 09805663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805663
System and method for caching data based on identity of requestor Mar 12, 2001 Issued
Array ( [id] => 5848367 [patent_doc_number] => 20020133666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'System latency levelization for read data' [patent_app_type] => new [patent_app_number] => 09/804221 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3512 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133666.pdf [firstpage_image] =>[orig_patent_app_number] => 09804221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804221
System latency levelization for read data Mar 12, 2001 Issued
Array ( [id] => 1186669 [patent_doc_number] => 06738876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Apparatus and method for preserving a region code for an optical disk drive' [patent_app_type] => B2 [patent_app_number] => 09/803927 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1821 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738876.pdf [firstpage_image] =>[orig_patent_app_number] => 09803927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803927
Apparatus and method for preserving a region code for an optical disk drive Mar 12, 2001 Issued
Array ( [id] => 5848375 [patent_doc_number] => 20020133672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Cache way prediction based on instruction base register' [patent_app_type] => new [patent_app_number] => 09/805384 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4320 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133672.pdf [firstpage_image] =>[orig_patent_app_number] => 09805384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805384
Cache way prediction based on instruction base register Mar 12, 2001 Issued
Array ( [id] => 6451232 [patent_doc_number] => 20020129209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers' [patent_app_type] => new [patent_app_number] => 09/749328 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5197 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129209.pdf [firstpage_image] =>[orig_patent_app_number] => 09749328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749328
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers Mar 11, 2001 Issued
Array ( [id] => 6703094 [patent_doc_number] => 20030225974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING THE EFFICIENCY OF CACHE MEMORIES USING CHAINED METRICS' [patent_app_type] => new [patent_app_number] => 09/804372 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6348 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225974.pdf [firstpage_image] =>[orig_patent_app_number] => 09804372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804372
Method and apparatus for improving the efficiency of cache memories using chained metrics Mar 11, 2001 Issued
Array ( [id] => 1418829 [patent_doc_number] => 06546470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation' [patent_app_type] => B1 [patent_app_number] => 09/749349 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546470.pdf [firstpage_image] =>[orig_patent_app_number] => 09749349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749349
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation Mar 11, 2001 Issued
Array ( [id] => 787580 [patent_doc_number] => 06990535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Device and method for multi-ported, single bus-mastering data buffer management' [patent_app_type] => utility [patent_app_number] => 09/793363 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5999 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990535.pdf [firstpage_image] =>[orig_patent_app_number] => 09793363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793363
Device and method for multi-ported, single bus-mastering data buffer management Feb 25, 2001 Issued
Array ( [id] => 1361163 [patent_doc_number] => 06587913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode' [patent_app_type] => B2 [patent_app_number] => 09/773300 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 45 [patent_no_of_words] => 15381 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587913.pdf [firstpage_image] =>[orig_patent_app_number] => 09773300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773300
Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode Jan 30, 2001 Issued
Array ( [id] => 5990115 [patent_doc_number] => 20020099765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Generational garbage collector with persistent object cache' [patent_app_type] => new [patent_app_number] => 09/681140 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7607 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099765.pdf [firstpage_image] =>[orig_patent_app_number] => 09681140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681140
Generational garbage collector with persistent object cache Jan 22, 2001 Issued
Array ( [id] => 1183576 [patent_doc_number] => 06751717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method and apparatus for clock synchronization between a system clock and a burst data clock' [patent_app_type] => B2 [patent_app_number] => 09/767490 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4081 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751717.pdf [firstpage_image] =>[orig_patent_app_number] => 09767490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767490
Method and apparatus for clock synchronization between a system clock and a burst data clock Jan 22, 2001 Issued
Array ( [id] => 1329186 [patent_doc_number] => 06606695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Method and apparatus for controlling access to storage device' [patent_app_type] => B2 [patent_app_number] => 09/764286 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6481 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606695.pdf [firstpage_image] =>[orig_patent_app_number] => 09764286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764286
Method and apparatus for controlling access to storage device Jan 18, 2001 Issued
Array ( [id] => 1169464 [patent_doc_number] => 06763424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Partial block data programming and reading operations in a non-volatile memory' [patent_app_type] => B2 [patent_app_number] => 09/766436 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7808 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763424.pdf [firstpage_image] =>[orig_patent_app_number] => 09766436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766436
Partial block data programming and reading operations in a non-volatile memory Jan 18, 2001 Issued
Array ( [id] => 1357079 [patent_doc_number] => 06591346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Mechanism for managing an object cache' [patent_app_type] => B1 [patent_app_number] => 09/765853 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4730 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591346.pdf [firstpage_image] =>[orig_patent_app_number] => 09765853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765853
Mechanism for managing an object cache Jan 18, 2001 Issued
Array ( [id] => 1423537 [patent_doc_number] => 06539460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'System and method for storing data sectors with header and trailer information in a disk cache supporting memory compression' [patent_app_type] => B2 [patent_app_number] => 09/765563 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7506 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539460.pdf [firstpage_image] =>[orig_patent_app_number] => 09765563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765563
System and method for storing data sectors with header and trailer information in a disk cache supporting memory compression Jan 18, 2001 Issued
Array ( [id] => 1339243 [patent_doc_number] => 06601145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls' [patent_app_type] => B2 [patent_app_number] => 09/749348 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5102 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601145.pdf [firstpage_image] =>[orig_patent_app_number] => 09749348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749348
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls Dec 26, 2000 Issued
Array ( [id] => 1418805 [patent_doc_number] => 06546468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update' [patent_app_type] => B2 [patent_app_number] => 09/749054 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546468.pdf [firstpage_image] =>[orig_patent_app_number] => 09749054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749054
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update Dec 26, 2000 Issued
Array ( [id] => 1411821 [patent_doc_number] => 06553477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Microprocessor and address translation method for microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/707347 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3962 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553477.pdf [firstpage_image] =>[orig_patent_app_number] => 09707347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/707347
Microprocessor and address translation method for microprocessor Nov 5, 2000 Issued
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