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Ngoclan Thi Mai

Examiner (ID: 11143, Phone: (571)272-1246 , Office: P/1733 )

Most Active Art Unit
1742
Art Unit(s)
1733, 2899, 3641, 5332, 2204, 1741, 1793, 1742, 1734
Total Applications
2444
Issued Applications
2034
Pending Applications
108
Abandoned Applications
302

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16609038 [patent_doc_number] => 10910051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Method and electronic circuit for verifying operation performed by cell of RRAM [patent_app_type] => utility [patent_app_number] => 16/686196 [patent_app_country] => US [patent_app_date] => 2019-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686196
Method and electronic circuit for verifying operation performed by cell of RRAM Nov 16, 2019 Issued
Array ( [id] => 15622463 [patent_doc_number] => 20200081636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => CONFIGURABLE MEMORY STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/685722 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685722
Configurable memory storage system Nov 14, 2019 Issued
Array ( [id] => 16668264 [patent_doc_number] => 10937517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Apparatuses and methods to encode column plane compression data [patent_app_type] => utility [patent_app_number] => 16/685186 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5367 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685186 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685186
Apparatuses and methods to encode column plane compression data Nov 14, 2019 Issued
Array ( [id] => 16447945 [patent_doc_number] => 10839876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Apparatuses and methods for clock leveling in semiconductor memories [patent_app_type] => utility [patent_app_number] => 16/685708 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685708 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685708
Apparatuses and methods for clock leveling in semiconductor memories Nov 14, 2019 Issued
Array ( [id] => 15872997 [patent_doc_number] => 20200143902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => DUAL TAP ARCHITECTURE FOR ENABLING SECURE ACCESS FOR DDR MEMORY TEST CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/675676 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675676 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675676
Dual tap architecture for enabling secure access for DDR memory test controller Nov 5, 2019 Issued
Array ( [id] => 16593650 [patent_doc_number] => 10902926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Charge pump and memory device including the same [patent_app_type] => utility [patent_app_number] => 16/675914 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9135 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675914
Charge pump and memory device including the same Nov 5, 2019 Issued
Array ( [id] => 15563871 [patent_doc_number] => 20200066347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE [patent_app_type] => utility [patent_app_number] => 16/669920 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669920
Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance Oct 30, 2019 Issued
Array ( [id] => 16699691 [patent_doc_number] => 10950299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => System and method for cryogenic hybrid technology computing and memory [patent_app_type] => utility [patent_app_number] => 16/666122 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 52 [patent_no_of_words] => 17439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666122
System and method for cryogenic hybrid technology computing and memory Oct 27, 2019 Issued
Array ( [id] => 16020407 [patent_doc_number] => 20200185047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/598922 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598922
Semiconductor memory device and operating method thereof Oct 9, 2019 Issued
Array ( [id] => 15745271 [patent_doc_number] => 20200111525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => METHODS FOR ROW HAMMER MITIGATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 16/597694 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597694
Methods for row hammer mitigation and memory devices and systems employing the same Oct 8, 2019 Issued
Array ( [id] => 16174320 [patent_doc_number] => 10715913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Neural network-based loudspeaker modeling with a deconvolution filter [patent_app_type] => utility [patent_app_number] => 16/570844 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5775 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570844
Neural network-based loudspeaker modeling with a deconvolution filter Sep 12, 2019 Issued
Array ( [id] => 16803080 [patent_doc_number] => 10998031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory [patent_app_type] => utility [patent_app_number] => 16/569588 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 12590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569588
Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory Sep 11, 2019 Issued
Array ( [id] => 16448368 [patent_doc_number] => 10840299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Resistive random access memory circuit [patent_app_type] => utility [patent_app_number] => 16/558630 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6099 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558630
Resistive random access memory circuit Sep 2, 2019 Issued
Array ( [id] => 16210141 [patent_doc_number] => 20200243131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/558430 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558430
Semiconductor storage device and operation method thereof Sep 2, 2019 Issued
Array ( [id] => 15872975 [patent_doc_number] => 20200143891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/557886 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557886
Memory system Aug 29, 2019 Issued
Array ( [id] => 16067179 [patent_doc_number] => 10692548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Address fault detection in a flash memory system [patent_app_type] => utility [patent_app_number] => 16/551593 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 8462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551593
Address fault detection in a flash memory system Aug 25, 2019 Issued
Array ( [id] => 16631389 [patent_doc_number] => 20210050042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => APPARATUSES AND METHODS FOR REDUCING ACCESS DEVICE SUB-THRESHOLD LEAKAGE IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/543240 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543240
Apparatuses and methods for reducing access device sub-threshold leakage in semiconductor devices Aug 15, 2019 Issued
Array ( [id] => 15597111 [patent_doc_number] => 20200075090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => PULSED APPLICATION OF WORDLINE UNDERDRIVE (WLUD) FOR ENHANCING STABILITY OF STATIC RANDOM ACCESS MEMORY (SRAM) OPERATION IN A LOW SUPPLY VOLTAGE ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 16/542432 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542432
PULSED APPLICATION OF WORDLINE UNDERDRIVE (WLUD) FOR ENHANCING STABILITY OF STATIC RANDOM ACCESS MEMORY (SRAM) OPERATION IN A LOW SUPPLY VOLTAGE ENVIRONMENT Aug 15, 2019 Abandoned
Array ( [id] => 16773766 [patent_doc_number] => 10984885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Memory test array and test method thereof [patent_app_type] => utility [patent_app_number] => 16/517690 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5957 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517690 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517690
Memory test array and test method thereof Jul 21, 2019 Issued
Array ( [id] => 16536240 [patent_doc_number] => 10878853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Power supply control [patent_app_type] => utility [patent_app_number] => 16/518256 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518256
Power supply control Jul 21, 2019 Issued
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