Search

Nguyen Tran

Examiner (ID: 7977, Phone: (571)270-1269 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2892, 2838
Total Applications
1484
Issued Applications
1176
Pending Applications
115
Abandoned Applications
219

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11944952 [patent_doc_number] => 20170249103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'DATA PROCESSING SYSTEM HAVING A WRITE REQUEST NETWORK AND A WRITE DATA NETWORK' [patent_app_type] => utility [patent_app_number] => 15/053248 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053248
Data processing system having a write request network and a write data network Feb 24, 2016 Issued
Array ( [id] => 13110235 [patent_doc_number] => 10073771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Data storage method and system thereof [patent_app_type] => utility [patent_app_number] => 15/052958 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4532 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052958
Data storage method and system thereof Feb 24, 2016 Issued
Array ( [id] => 11086427 [patent_doc_number] => 20160283393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'INFORMATION PROCESSING APPARATUS, STORAGE DEVICE CONTROL METHOD, AND INFORMATION PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/052942 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5681 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052942 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052942
Information processing apparatus and control method for dynamic cache management Feb 24, 2016 Issued
Array ( [id] => 11944950 [patent_doc_number] => 20170249101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SYNCHRONIZING A CURSOR BASED ON CONSUMER AND PRODUCER THROUGHPUTS' [patent_app_type] => utility [patent_app_number] => 15/052994 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052994 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052994
Synchronizing a cursor based on consumer and producer throughputs Feb 24, 2016 Issued
Array ( [id] => 13185957 [patent_doc_number] => 10108498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Virtual machine backup [patent_app_type] => utility [patent_app_number] => 15/048101 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10707 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/048101
Virtual machine backup Feb 18, 2016 Issued
Array ( [id] => 10802496 [patent_doc_number] => 20160148653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD AND APPARATUS FOR USING A PRE-CLOCK ENABLE COMMAND FOR POWER MANAGEMENT MODES' [patent_app_type] => utility [patent_app_number] => 15/011383 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011383
METHOD AND APPARATUS FOR USING A PRE-CLOCK ENABLE COMMAND FOR POWER MANAGEMENT MODES Jan 28, 2016 Abandoned
Array ( [id] => 10801521 [patent_doc_number] => 20160147678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD AND APPARATUS FOR SELECTING ONE OF A PLURALITY OF BUS INTERFACE CONFIGURATIONS TO USE' [patent_app_type] => utility [patent_app_number] => 15/011375 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12026 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011375
Method and apparatus for selecting one of a plurality of bus interface configurations to use Jan 28, 2016 Issued
Array ( [id] => 10786113 [patent_doc_number] => 20160132269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'METHOD AND APPARATUS FOR SETTING HIGH ADDRESS BITS IN A MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 14/995145 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12009 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995145
Method and apparatus for setting high address bits in a memory module Jan 12, 2016 Issued
Array ( [id] => 11745625 [patent_doc_number] => 20170199698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'INTRA-STORAGE DEVICE DATA TIERING' [patent_app_type] => utility [patent_app_number] => 14/991444 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/991444
INTRA-STORAGE DEVICE DATA TIERING Jan 7, 2016 Abandoned
Array ( [id] => 11745606 [patent_doc_number] => 20170199679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SYSTEM AND METHOD FOR USING PERSISTENT MEMORY TO ACCELERATE WRITE PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/990269 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990269
System and method for using persistent memory to accelerate write performance Jan 6, 2016 Issued
Array ( [id] => 11745621 [patent_doc_number] => 20170199694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SYSTEMS AND METHODS FOR DYNAMIC STORAGE ALLOCATION AMONG STORAGE SERVERS' [patent_app_type] => utility [patent_app_number] => 14/990499 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5202 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990499
SYSTEMS AND METHODS FOR DYNAMIC STORAGE ALLOCATION AMONG STORAGE SERVERS Jan 6, 2016 Abandoned
Array ( [id] => 14122991 [patent_doc_number] => 10248353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Dynamicly freeing storage space in tiered storage systems [patent_app_type] => utility [patent_app_number] => 14/990695 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6061 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990695
Dynamicly freeing storage space in tiered storage systems Jan 6, 2016 Issued
Array ( [id] => 12513423 [patent_doc_number] => 10001938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Systems and methods for optimized utilization of storage resources based on performance and power characteristics [patent_app_type] => utility [patent_app_number] => 14/990453 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990453 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990453
Systems and methods for optimized utilization of storage resources based on performance and power characteristics Jan 6, 2016 Issued
Array ( [id] => 11013117 [patent_doc_number] => 20160210070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND FLASH MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/990668 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990668
INFORMATION PROCESSING APPARATUS AND FLASH MEMORY CONTROL METHOD Jan 6, 2016 Abandoned
Array ( [id] => 15486463 [patent_doc_number] => 10558582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Technologies for execute only transactional memory [patent_app_type] => utility [patent_app_number] => 14/974972 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 19781 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974972 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974972
Technologies for execute only transactional memory Dec 17, 2015 Issued
Array ( [id] => 13891517 [patent_doc_number] => 10198306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Method and apparatus for a memory module to accept a command in multiple parts [patent_app_type] => utility [patent_app_number] => 14/967230 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 11642 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967230 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967230
Method and apparatus for a memory module to accept a command in multiple parts Dec 10, 2015 Issued
Array ( [id] => 10752043 [patent_doc_number] => 20160098195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING A TIMING ADJUSTMENT OF OUTPUT TO A HOST MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/967210 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12009 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967210 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967210
Method and apparatus for determining a timing adjustment of output to a host memory controller Dec 10, 2015 Issued
Array ( [id] => 10752214 [patent_doc_number] => 20160098366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD AND APPARATUS FOR ENCODING REGISTERS IN A MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 14/967226 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967226 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967226
Method and apparatus for encoding registers in a memory module Dec 10, 2015 Issued
Array ( [id] => 13807271 [patent_doc_number] => 10180902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Pauseless location and object handle based garbage collection [patent_app_type] => utility [patent_app_number] => 14/941558 [patent_app_country] => US [patent_app_date] => 2015-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 10501 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941558 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941558
Pauseless location and object handle based garbage collection Nov 13, 2015 Issued
Array ( [id] => 11889832 [patent_doc_number] => 09760393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Storage architecture for virtual machines' [patent_app_type] => utility [patent_app_number] => 14/937453 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 15182 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937453 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/937453
Storage architecture for virtual machines Nov 9, 2015 Issued
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