Search

Nha T. Nguyen

Examiner (ID: 16503, Phone: (571)270-1405 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1176
Issued Applications
996
Pending Applications
55
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19327299 [patent_doc_number] => 12044981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Method and apparatus for optimization of lithographic process [patent_app_type] => utility [patent_app_number] => 17/381817 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381817
Method and apparatus for optimization of lithographic process Jul 20, 2021 Issued
Array ( [id] => 20331178 [patent_doc_number] => 12461451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Computational metrology [patent_app_type] => utility [patent_app_number] => 17/379662 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 25186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379662
Computational metrology Jul 18, 2021 Issued
Array ( [id] => 18957692 [patent_doc_number] => 20240046019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHOD AND DEVICE FOR DESIGNING GATE DRIVING CIRCUIT, CONTROLLER, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/427096 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/427096
METHOD AND DEVICE FOR DESIGNING GATE DRIVING CIRCUIT, CONTROLLER, AND STORAGE MEDIUM Jul 15, 2021 Issued
Array ( [id] => 19259905 [patent_doc_number] => 12019964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-25 [patent_title] => Optimizing use of computer resources in implementing circuit designs through machine learning [patent_app_type] => utility [patent_app_number] => 17/376892 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376892
Optimizing use of computer resources in implementing circuit designs through machine learning Jul 14, 2021 Issued
Array ( [id] => 17189576 [patent_doc_number] => 20210336461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => ON-BOARD CHARGING STATION FOR A REMOTE CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 17/305463 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305463
On-board charging station for a remote control device Jul 7, 2021 Issued
Array ( [id] => 19911921 [patent_doc_number] => 12288132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Active stabilization of coherent controllers using nearby qubits [patent_app_type] => utility [patent_app_number] => 17/362810 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4485 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362810
Active stabilization of coherent controllers using nearby qubits Jun 28, 2021 Issued
Array ( [id] => 18873475 [patent_doc_number] => 11861286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Segregating defects based on computer-aided design (CAD) identifiers associated with the defects [patent_app_type] => utility [patent_app_number] => 17/362085 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7218 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362085
Segregating defects based on computer-aided design (CAD) identifiers associated with the defects Jun 28, 2021 Issued
Array ( [id] => 17276849 [patent_doc_number] => 20210383047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => GUIDING SAMPLE SIZE CHOICE IN ANALOG DEFECT OR FAULT SIMULATION [patent_app_type] => utility [patent_app_number] => 17/339186 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339186
Guiding sample size choice in analog defect or fault simulation Jun 3, 2021 Issued
Array ( [id] => 18062406 [patent_doc_number] => 20220393493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => BATTERY MANAGEMENT FOR PERFORMING A FINAL ACTION [patent_app_type] => utility [patent_app_number] => 17/303599 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303599
Battery management for performing a final action Jun 2, 2021 Issued
Array ( [id] => 17637190 [patent_doc_number] => 11347914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => System and method for automatic performance analysis in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/337984 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5551 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337984
System and method for automatic performance analysis in an electronic circuit design Jun 2, 2021 Issued
Array ( [id] => 18047008 [patent_doc_number] => 11520964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Method and system for assertion-based formal verification using unique signature values [patent_app_type] => utility [patent_app_number] => 17/336315 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5461 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336315
Method and system for assertion-based formal verification using unique signature values Jun 1, 2021 Issued
Array ( [id] => 17099393 [patent_doc_number] => 20210287184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => Methods for Cloud Processing of Vehicle Diagnostics [patent_app_type] => utility [patent_app_number] => 17/329935 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329935
Methods for cloud processing of vehicle diagnostics May 24, 2021 Issued
Array ( [id] => 17025416 [patent_doc_number] => 20210249288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/244084 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244084
Optimizating semiconductor binning by feed-forward process adjustment Apr 28, 2021 Issued
Array ( [id] => 18438710 [patent_doc_number] => 20230186005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => VIRTUAL ENVIRONMENT FOR IMPLEMENTING INTEGRATED PHOTONICS ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/922321 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17922321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/922321
Virtual environment for implementing integrated photonics assemblies Apr 28, 2021 Issued
Array ( [id] => 19355982 [patent_doc_number] => 12056430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Methods of routing clock trees, integrated circuits and methods of designing integrated circuits [patent_app_type] => utility [patent_app_number] => 17/238874 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 13414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/238874
Methods of routing clock trees, integrated circuits and methods of designing integrated circuits Apr 22, 2021 Issued
Array ( [id] => 17172836 [patent_doc_number] => 20210326506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => METHOD AND SYSTEM FOR CUSTOM MODEL DEFINITION OF ANALOG DEFECTS IN AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/235605 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235605
Method and system for custom model definition of analog defects in an integrated circuit Apr 19, 2021 Issued
Array ( [id] => 19639069 [patent_doc_number] => 12169677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Standard cell layout generation with applied artificial intelligence [patent_app_type] => utility [patent_app_number] => 17/230592 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230592
Standard cell layout generation with applied artificial intelligence Apr 13, 2021 Issued
Array ( [id] => 16980210 [patent_doc_number] => 20210224447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => GROUPING OF PAULI STRINGS USING ENTANGLED MEASUREMENTS [patent_app_type] => utility [patent_app_number] => 17/225691 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225691
Grouping of Pauli strings using entangled measurements Apr 7, 2021 Issued
Array ( [id] => 17916083 [patent_doc_number] => 20220318479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SHADOW FEATURE-BASED DETERMINATION OF CAPACITANCE VALUES FOR INTEGRATED CIRCUIT (IC) LAYOUTS [patent_app_type] => utility [patent_app_number] => 17/218694 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218694
Shadow feature-based determination of capacitance values for integrated circuit (IC) layouts Mar 30, 2021 Issued
Array ( [id] => 19259073 [patent_doc_number] => 12019124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Charge measurement calibration in a system using a pulse frequency modulated DC-DC converter [patent_app_type] => utility [patent_app_number] => 17/215723 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215723
Charge measurement calibration in a system using a pulse frequency modulated DC-DC converter Mar 28, 2021 Issued
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