Search

Nicholas A. Ros

Examiner (ID: 17108)

Most Active Art Unit
3754
Art Unit(s)
3754, 3751
Total Applications
632
Issued Applications
325
Pending Applications
77
Abandoned Applications
254

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14036415 [patent_doc_number] => 10229964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 15/832628 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 26280 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832628
Display device Dec 4, 2017 Issued
Array ( [id] => 12631392 [patent_doc_number] => 20180102294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 15/828822 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828822
Integrated circuit with replacement gate stacks and method of forming same Nov 30, 2017 Issued
Array ( [id] => 12615210 [patent_doc_number] => 20180096900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 15/828802 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828802
Integrated circuit with replacement gate stacks and method of forming same Nov 30, 2017 Issued
Array ( [id] => 15946851 [patent_doc_number] => 10661308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => High displacement ultrasonic transducer [patent_app_type] => utility [patent_app_number] => 15/817360 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 9725 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817360
High displacement ultrasonic transducer Nov 19, 2017 Issued
Array ( [id] => 14079501 [patent_doc_number] => 20190088638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => INTEGRATED CIRCUITS WITH STANDARD CELL [patent_app_type] => utility [patent_app_number] => 15/785447 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785447
Integrated circuits with standard cell Oct 16, 2017 Issued
Array ( [id] => 13451867 [patent_doc_number] => 20180277476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 15/785511 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785511
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME Oct 16, 2017 Abandoned
Array ( [id] => 14178251 [patent_doc_number] => 10263148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Light emitting diode structure [patent_app_type] => utility [patent_app_number] => 15/785507 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2143 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785507
Light emitting diode structure Oct 16, 2017 Issued
Array ( [id] => 14558205 [patent_doc_number] => 10347573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Semiconductor device and wiring board design method [patent_app_type] => utility [patent_app_number] => 15/782365 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4569 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782365
Semiconductor device and wiring board design method Oct 11, 2017 Issued
Array ( [id] => 15139903 [patent_doc_number] => 10483440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Cadmium-free quantum dot nanoparticles [patent_app_type] => utility [patent_app_number] => 15/725768 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3984 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725768
Cadmium-free quantum dot nanoparticles Oct 4, 2017 Issued
Array ( [id] => 13392663 [patent_doc_number] => 20180247874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION [patent_app_type] => utility [patent_app_number] => 15/723528 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723528
Integrated circuit with improved resistive region Oct 2, 2017 Issued
Array ( [id] => 14137859 [patent_doc_number] => 20190103319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE LENGTHS AND A RESULTING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/723472 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723472
Method of forming vertical field effect transistors with different gate lengths and a resulting structure Oct 2, 2017 Issued
Array ( [id] => 12823345 [patent_doc_number] => 20180166287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE USING TITANIUM-CONTAINING LAYER AND DEVICE FORMED [patent_app_type] => utility [patent_app_number] => 15/723541 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723541
Method of forming semiconductor device using titanium-containing layer and device formed Oct 2, 2017 Issued
Array ( [id] => 13320889 [patent_doc_number] => 20180211982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/723499 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723499
Display substrate, manufacturing method thereof, and display panel Oct 2, 2017 Issued
Array ( [id] => 16425225 [patent_doc_number] => 20200350423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => QUANTUM WELL STACKS FOR QUANTUM DOT DEVICES [patent_app_type] => utility [patent_app_number] => 16/642886 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16642886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/642886
Quantum well stacks for quantum dot devices Sep 27, 2017 Issued
Array ( [id] => 14252645 [patent_doc_number] => 10276530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Laterally extended conductive bump buffer [patent_app_type] => utility [patent_app_number] => 15/707145 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707145
Laterally extended conductive bump buffer Sep 17, 2017 Issued
Array ( [id] => 12181689 [patent_doc_number] => 20180040625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'COMPLEMENTARY SONOS INTEGRATION INTO CMOS FLOW' [patent_app_type] => utility [patent_app_number] => 15/708008 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8741 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708008 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708008
Complementary SONOS integration into CMOS flow Sep 17, 2017 Issued
Array ( [id] => 13019671 [patent_doc_number] => 10032955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Quantum dot having core-shell structure [patent_app_type] => utility [patent_app_number] => 15/698047 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6562 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698047
Quantum dot having core-shell structure Sep 6, 2017 Issued
Array ( [id] => 13349621 [patent_doc_number] => 20180226350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/689659 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689659
Fan-out semiconductor package Aug 28, 2017 Issued
Array ( [id] => 14221729 [patent_doc_number] => 20190123249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ULTRAVIOLET LIGHT-EMITTING ELEMENT AND NITRIDE SEMICONDUCTOR ULTRAVIOLET LIGHT-EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 15/772612 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15772612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/772612
Method for manufacturing nitride semiconductor ultraviolet light-emitting element and nitride semiconductor ultraviolet light-emitting element Aug 23, 2017 Issued
Array ( [id] => 15250137 [patent_doc_number] => 10510597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Methods for hybrid wafer bonding integrated with CMOS processing [patent_app_type] => utility [patent_app_number] => 15/670786 [patent_app_country] => US [patent_app_date] => 2017-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15670786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/670786
Methods for hybrid wafer bonding integrated with CMOS processing Aug 6, 2017 Issued
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