Search

Nicholas A. Smith

Examiner (ID: 15161, Phone: (571)272-8760 , Office: P/1754 )

Most Active Art Unit
1754
Art Unit(s)
1754, 4145, 1723, 1795, 1794, 1752, 1753, 4100, 1742
Total Applications
1294
Issued Applications
796
Pending Applications
89
Abandoned Applications
418

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16858121 [patent_doc_number] => 20210158866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => METHOD AND SYSTEM TO IMPROVE READ RELIABILITY IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/692263 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692263
Method and system to improve read reliability in memory devices Nov 21, 2019 Issued
Array ( [id] => 16788970 [patent_doc_number] => 10991407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/692903 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16133 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692903 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692903
Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same Nov 21, 2019 Issued
Array ( [id] => 15659173 [patent_doc_number] => 20200092117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => DETECTING UNRELIABLE BITS IN TRANSISTOR CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/689264 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689264
Detecting unreliable bits in transistor circuitry Nov 19, 2019 Issued
Array ( [id] => 17195878 [patent_doc_number] => 11164643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Non-volatile memory device and programming method thereof [patent_app_type] => utility [patent_app_number] => 16/686567 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 11860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686567
Non-volatile memory device and programming method thereof Nov 17, 2019 Issued
Array ( [id] => 16210153 [patent_doc_number] => 20200243143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ERASING METHOD [patent_app_type] => utility [patent_app_number] => 16/684591 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684591
Erasing method Nov 14, 2019 Issued
Array ( [id] => 16385648 [patent_doc_number] => 10810489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models [patent_app_type] => utility [patent_app_number] => 16/680506 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6630 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680506
Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models Nov 11, 2019 Issued
Array ( [id] => 17572740 [patent_doc_number] => 11321008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Temperature-based memory management [patent_app_type] => utility [patent_app_number] => 16/674955 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674955 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674955
Temperature-based memory management Nov 4, 2019 Issued
Array ( [id] => 16446735 [patent_doc_number] => 10838662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Memory system and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/601128 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 12289 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601128
Memory system and method of operating the same Oct 13, 2019 Issued
Array ( [id] => 15839969 [patent_doc_number] => 20200135267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => ORTHOGONAL DUAL PORT RAM (ORAM) [patent_app_type] => utility [patent_app_number] => 16/584257 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584257
Orthogonal dual port ram (ORAM) Sep 25, 2019 Issued
Array ( [id] => 18204490 [patent_doc_number] => 11586887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Neural network apparatus [patent_app_type] => utility [patent_app_number] => 16/556362 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5526 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556362
Neural network apparatus Aug 29, 2019 Issued
Array ( [id] => 16355093 [patent_doc_number] => 10795603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Systems and methods for writing zeros to a memory array [patent_app_type] => utility [patent_app_number] => 16/555852 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6634 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555852
Systems and methods for writing zeros to a memory array Aug 28, 2019 Issued
Array ( [id] => 19078445 [patent_doc_number] => 11947813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Configurable memory die capacitance [patent_app_type] => utility [patent_app_number] => 16/976286 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18626 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/976286
Configurable memory die capacitance Aug 28, 2019 Issued
Array ( [id] => 15259679 [patent_doc_number] => 20190378573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => BOOSTED CHANNEL PROGRAMMING OF MEMORY [patent_app_type] => utility [patent_app_number] => 16/546417 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546417
Boosted channel programming of memory Aug 20, 2019 Issued
Array ( [id] => 15217457 [patent_doc_number] => 20190371415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => CIRCUIT HAVING A LOW POWER CHARGE PUMP FOR STORING INFORMATION IN NON-VOLATILE MEMORY DURING A LOSS OF POWER EVENT [patent_app_type] => utility [patent_app_number] => 16/543867 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543867
Circuit having a low power charge pump for storing information in non-volatile memory during a loss of power event Aug 18, 2019 Issued
Array ( [id] => 15214877 [patent_doc_number] => 20190370125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => CIRCUIT AND METHOD FOR STORING INFORMATION IN NON-VOLATILE MEMORY DURING A LOSS OF POWER EVENT [patent_app_type] => utility [patent_app_number] => 16/540409 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540409
Circuit and method for storing information in non-volatile memory during a loss of power event Aug 13, 2019 Issued
Array ( [id] => 15184367 [patent_doc_number] => 20190362775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => APPARATUSES AND METHODS FOR REFRESHING MEMORY OF A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/538603 [patent_app_country] => US [patent_app_date] => 2019-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16538603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/538603
Apparatuses and methods for refreshing memory of a semiconductor device Aug 11, 2019 Issued
Array ( [id] => 15092549 [patent_doc_number] => 20190341086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/517185 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517185
Semiconductor devices Jul 18, 2019 Issued
Array ( [id] => 17380886 [patent_doc_number] => 11238907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Techniques for precharging a memory cell [patent_app_type] => utility [patent_app_number] => 16/512999 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17435 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512999
Techniques for precharging a memory cell Jul 15, 2019 Issued
Array ( [id] => 15027743 [patent_doc_number] => 20190324876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => FLASH MEMORY BLOCK RETIREMENT POLICY [patent_app_type] => utility [patent_app_number] => 16/504067 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/504067
Flash memory block retirement policy Jul 4, 2019 Issued
Array ( [id] => 16926956 [patent_doc_number] => 11048439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Device of memory modules [patent_app_type] => utility [patent_app_number] => 16/448557 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1634 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448557 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448557
Device of memory modules Jun 20, 2019 Issued
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